Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

PSoC™ 5, 3 & 1 Forum Discussions

LeKu_697901
Level 2
Level 2

Hello.

The customer board includes CY8C3866LTI-030/DIE device.

I'm trying to build Boundary Scan test for this board with JTAG Technologies Provision tool.

The system does not recognize the device. (All ones on TDO).

By PSoC3 programmer with MiniProg3 adapter in JTAG mode the device recognized with IR=4, DR=35. Please look attached file.

But by the BSDL file it includes 137 bits DR.

We have checked all lines by scope and TMS, TCK, TDI lines looks good with 1.8V level. But TDO line is no active.

What wrong?

Any help will be appreciable.

0 Likes
11 Replies
DheerajK_81
Moderator
Moderator
Moderator
First comment on KBA First comment on blog 5 questions asked

Can you please refer to this KBA to check if you are loading the right BSDL file based on the configuration: PSoC® 3, PSoC 4 and PSoC 5 BSDL Files - KBA84780 ?

Regards,

Dheeraj

0 Likes

Dear DheerajK_81,

I checked and found that I really used old BSDL file.

Thank you.

My device is CY8C3866LTI-030/DIE.

So by the updated BSDL file CY8C3XXXX_XXX_QFN48_4JTAG.bsdl

the BSR length should be 139.

  attribute BOUNDARY_LENGTH of CY8C3XXXX_XXX : entity is 139;

By the PSoC Programmer I received DR: 35.

PSoc Programmer view.JPG

Could you explain it?

The device is still invisible by JTAG Technologies Provision software.

0 Likes

Looks like I found the problem.

In the customer’s design, line TSRT was connected to XRES pin of the device, not to dedicated TRST for 5-wires JTAG connection.

I paid attention that if run Infra test immediately after “Scan Bus” command in PSoC Programmer, the test passes one time, exclude TRST test.

Using 4-wire or 5-wire BSDL files had not any effect.

After I disconnected TRST line from XRES pin, the Infra test started to pass stable with 4-wire BSDL file.Infra_Test.JPG

BSREG_test.JPG

The issue is closed.

0 Likes

Sorry, the issue still not closed.

Now, by behavior of Interconnection test I see that only few pins toggled according the BSDL file.

These pins are 30 (P3_1), 31 (P3_2), 36 (P3_6), 37 (P3_7).

Looks like BSR cells order wrong.

Was the BSDL file validated?

0 Likes

Can you please let me know which BSDL file you are referring to here? It is validated, but I can test it again just to confirm.

Regards,
Dheeraj

0 Likes

CY8C3XXXX_XXX_QFN68_4JTAG.bsdl

0 Likes

May be need any Compliance Pattern or a preliminary configuration by SVF?

0 Likes

Hello Dheeraj,

Do you have any news about the issue?

Sorry, but it is very urgent issue.

Thank you.

0 Likes

Can you please share the schematic of your design? We are looking into the BSDL files, will get back to you as soon as possible.


Regards,
Dheeraj

0 Likes

Please send me your personal e-mail.address

0 Likes
0 Likes