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Hi,
I want to add some logic wrapped to the CAN component for FD tolerant operation as mentioned in https://can-newsletter.org/uploads/media/raw/35a48f1d88ddf2a198638c0a5be51761.pdf .
The design is mostly done,
Tx output switching is OK with a tristate output pin (thanks to the transceiver pull-up)
but I have a problem with rx input switching. The error message is;
Error: mpr.M0074: The RX port on CAN block "\CAN:CanIP\" must be directly connected to an IO pin. (App=cydsfit)
It's working with the following way, but it wastes a pin;
Do you have any idea to do it without any wasted pin? Is there any way to remove the rx pin constraint of CAN component?
( same issue : CAN-BUS: 2 controllers in 1 chip => 1 transceiver, how to do it? )
Thanks, Regards.
Solved! Go to Solution.
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Hi,
I have finished the design. It works in my case and everything looks like OK. Further improvements may be done but I will not be able to spend more time. Further tests should be done also. I'm uploading the design here as a workspace. Anyone can use it for any purpose with their own responsibility.
Any test result, bug report/fix, improvement is welcome.
Maybe Cypress guys add this to the CAN component as a checkbox like "Enable FD Tolerant Operation" with cleaner method.
If CAN IP have other IOs that we can't see, further improvements could be done. For example;
If it have bus idle, bit clock or stuff bit signals accesssible then these are reusable and some resurces can be saved.
And it would be good if Cypress adds to a "non - pin constrained" version for the CAN component or primitive.
Regards.
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Hi,
This is a design limitation imposed by the author of the CAN component.
Submit your idea for making the CAN component CAN-FD tolerant to Cypress. They may be interested.
A more complicated way is to import the CAN component into your design.
Next modify the code that requires it to be directly connected to a pin.
Or ...
Modify the CAN_v3_0.cysch file to include the "AND" gate and a new input "FD_frame". This should get around the "must be attached to a pin" requirement.
Just some thoughts.
Len
"Engineering is an Art. The Art of Compromise."
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Hi Len,
Thanks for your reply.
Adding "AND" in the component symbol didn't solve the problem.
The restriction comes from inside of the "cy_psoc3_can_v1_0" primitive.
Directly instantiating the primitive in the top schematic also gives the same result.
I couldn't find any related parameter in the primitive symbol/pin properties.
Thanks, Regards.
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Thanks for the feedback.
I imported the cy_psoc3_can. There appears to be no control of this component primitive for the user. Sorry I couldn't be of more help.
Len
"Engineering is an Art. The Art of Compromise."
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Hi,
I have finished the design. It works in my case and everything looks like OK. Further improvements may be done but I will not be able to spend more time. Further tests should be done also. I'm uploading the design here as a workspace. Anyone can use it for any purpose with their own responsibility.
Any test result, bug report/fix, improvement is welcome.
Maybe Cypress guys add this to the CAN component as a checkbox like "Enable FD Tolerant Operation" with cleaner method.
If CAN IP have other IOs that we can't see, further improvements could be done. For example;
If it have bus idle, bit clock or stuff bit signals accesssible then these are reusable and some resurces can be saved.
And it would be good if Cypress adds to a "non - pin constrained" version for the CAN component or primitive.
Regards.
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I appreciate your hard work and for sharing your insights on how the CAN component might be updated for CAN-FD.
Len
"Engineering is an Art. The Art of Compromise."
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Hi user_294846,
We really appreciate your commitment to post your solution to our community.
Since PSoC 5 is a old device, we might not be able to provide upgrades (hardware/ software) in the near future.
We highly recommend you to use our latest PSoC 6 device that supports CAN- FD in hardware. Please feel free to evaluate our PSoC 6 device for your application.
https://www.cypress.com/file/151476/download
Thanks for your valuable contribution to our community.
Regards,
Bragadeesh
Bragadeesh