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DeSi_1418406
Level 1
Level 1
5 sign-ins First like received 5 replies posted

Hi, I am currently using the CY8C5888AXI-LP096 for a project.  I have connected the XRES(Pin 15) line to a port for programming so that I can support programming in the field.

During testing, i found that the line can glitch, which seems to cause instability in my design.

Is there a way to disable the XRES line during normal operation?

I was reading some documentation and it mentioned that in the NV Latch register I could toggle the XRES to a GPIO pin.  But Looking through my code base, I can't seem to access the NV Latch register.  How do I access the NV Latch register?

I have tried using the optional XRES setting, but that changes pin#22 to the XRES line, and what i am looking for is how can I disable the XRES on pin #15.

If there is no way to disable (pin#15 XRES), what would you recommend to do to stabilize my system, but still have the capability to program the MCU?

 

Any help would be appreciated.

Thank you.

 

1 Solution
MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Hi,


You can access RESET_SR0 as CYREG_RESET_SR0 in PSoC Creator.


But for cortex-M3, DHCSR may provide the information you want 
the register seems to be accessed as CYREG_CORE_DBG_HLT_CS in PSoC Creator.


moto


P.S. BTW, I wonder if you can pull-up XRES exetrnally or disconnect XRES during the programming.

 

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4 Replies
Rohan_M
Moderator
Moderator
Moderator
50 solutions authored 25 likes received 250 sign-ins

Hi @DeSi_1418406 .

We can't disable the pin 15 XRES. I would recommend to try using XRES of pin 22. To answer your question on how  to configure NVL, please refer the below document.

https://www.infineon.com/dgdl/Infineon-CY8C58LP_CY8C56LP_CY8C54LP_CY8C52LP_PSOC_5LP_DEVICE_PROGRAMMI...

 

Let me know if you've more queries.

Regards,

Rohan

 

DeSi_1418406
Level 1
Level 1
5 sign-ins First like received 5 replies posted

Thank you for the answer.

Since XRES is constantly on.

How do I access the RESET_SR0 register, and if my system was accidentally reset via XRES from a hardware glitch.  Does the RESET_SR0 register set a flag notifying me that the XRES was activated?

 

 

0 Likes
MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Hi,


You can access RESET_SR0 as CYREG_RESET_SR0 in PSoC Creator.


But for cortex-M3, DHCSR may provide the information you want 
the register seems to be accessed as CYREG_CORE_DBG_HLT_CS in PSoC Creator.


moto


P.S. BTW, I wonder if you can pull-up XRES exetrnally or disconnect XRES during the programming.

 

Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

@DeSi_1418406 ,

Pin 15 XRES_N is a hard-coded pin.  It has an internal pull-up of about 5K ohms.

It is your responsibility to HW-condition the XRES_N signal.   (You mentioned glitches occurring on this signal).

One common way to HW-condition is to place a cap from the pin to GND.   This will dampen quick glitches with the RC constant formed by the 5K and the cap value.

Also, reprogramming can abandon the use of XRES_N all together.  However, this requires control of the power to the target PSoC in what is called power-cycling.

Len
"Engineering is an Art. The Art of Compromise."