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yaga_3967241
Level 3
Level 3
50 sign-ins 25 sign-ins 10 replies posted

Hello,

We are using PSoC LP5. There is one pin, which is set to digital input, Strong drive drive mode, Initial drive state 0. In the reset tab, Power-On reset is Don't care.

My questions are:

1. How does "Strong drive" drive mode work on an input pin? Does PSoC drive the pin to low(Initial drive state set to 0)? Or is it floating if there is no connection to any other components?

2. If all pins in this same port have power-on reset set to Don't care, the what is the value used?

Thanks,

Winston

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1 Solution
Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

Winston,


1. How does "Strong drive" drive mode work on an input pin? Does PSoC drive the pin to low(Initial drive state set to 0)? Or is it floating if there is no connection to any other components?


It is possible to describe a pin as being both digital input AND a digital output as seen in the pin configuration below.

Len_CONSULTRON_0-1681480352139.png

The reality is that virtually any GPIO pin can be read as a digital input without configuring as such.  This is because each pin has a bit in a digital input register that cannot be turned off even if configured as an output or analog input.   Using the <Pin_x>_Read() function should return the pins digital value from this register.

Therefore unless the "HW connection" in the "Digital Input" is needed, there is no need to set it to "Digital Input".

Since your configuration has it as a digital output, this is the overriding characteristic.   It is also configured as a Strong drive initially set to low ('0').

In effect, AFTER power up before your code enters main(), the value of the output will be '0' and any digital reads of this pin will read '0' until your code changes the output value to '1' using <Pin_x>_Write(1).  At that time, the digital input will read '1'.

Note:  Because you have set the output to "Strong drive", DO NOT try to drive this pin externally.  This might cause pin damage if driven to an opposite value to that set internally.

If you need the output to be a "wired-OR" configuration where an external circuit can also drive this pin, set the drive mode to either "Open drain, drives low" if you're using an external resistor or "Resistive pull up" if you plan to use the PSoC's internal resistor.   In either case, this would allow your external drive circuit to safely share this pin and the digital value would be available when reading the pin using <Pin_x>_Read().


2. If all pins in this same port have power-on reset set to Don't care, the what is the value used?

 

Normally at reset, by default, all pins are configured to analog Hi-Z.  This means that at reset all pins will not be biased to a '0' or '1' state internally.   Depending on how the pin's circuit is configured externally, it might cause a 'glitch' in the pin's value until it gets configured as desired shortly after reset and before main().   You have to determine if this would adversely effect your circuit design.

As a potential 'fix', the "Power-on Reset:" field on the "Reset" tab allows for you to pre-bias the pin at power on reset to either a '0' or a '1'.   By default, the "Power-on Reset:" is set to "Don't Care" which means that the current pin's bias setting is left "as is" and is not changed.   The PSoCs as they come from the factory are set to "Analog Hi-Z".   

However, you can change this setting to specifically bias the pin at reset.

If you set it to "Analog Hi-Z" (which is the factory default), the pin will 'float' at reset potentially causing a 'glitch'.    For example if this output is used to drive the input to a FET, a floating state may turn on or off the FET which might be unacceptable.  The two bias mode below may help to keep the FET 'happy' in the event of a power-up reset, software reset or watchdog reset.

If you set it to "Pulled-Up", the internal pull-up bias resistor (~3K to 8K) will be enabled.  This resistance may be sufficient enough to prevent a glitch.  You need to confirm in your design.

If you set it to "Pulled-Down", the internal pull-down bias resistor (~3K to 8K) will be enabled.  This resistance may be sufficient enough to prevent a glitch.  You need to confirm in your design.

Note:  The non-volatile latch that stores this value internally has a limited write endurance cycle.  Therefore it is cautioned to prevent over use of this feature.  This is especially true on PSoCs used as parts during the development cycle.   Overuse may result in the part not maintaining its desired power reset state,

Len
"Engineering is an Art. The Art of Compromise."

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3 Replies
Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

Winston,


1. How does "Strong drive" drive mode work on an input pin? Does PSoC drive the pin to low(Initial drive state set to 0)? Or is it floating if there is no connection to any other components?


It is possible to describe a pin as being both digital input AND a digital output as seen in the pin configuration below.

Len_CONSULTRON_0-1681480352139.png

The reality is that virtually any GPIO pin can be read as a digital input without configuring as such.  This is because each pin has a bit in a digital input register that cannot be turned off even if configured as an output or analog input.   Using the <Pin_x>_Read() function should return the pins digital value from this register.

Therefore unless the "HW connection" in the "Digital Input" is needed, there is no need to set it to "Digital Input".

Since your configuration has it as a digital output, this is the overriding characteristic.   It is also configured as a Strong drive initially set to low ('0').

In effect, AFTER power up before your code enters main(), the value of the output will be '0' and any digital reads of this pin will read '0' until your code changes the output value to '1' using <Pin_x>_Write(1).  At that time, the digital input will read '1'.

Note:  Because you have set the output to "Strong drive", DO NOT try to drive this pin externally.  This might cause pin damage if driven to an opposite value to that set internally.

If you need the output to be a "wired-OR" configuration where an external circuit can also drive this pin, set the drive mode to either "Open drain, drives low" if you're using an external resistor or "Resistive pull up" if you plan to use the PSoC's internal resistor.   In either case, this would allow your external drive circuit to safely share this pin and the digital value would be available when reading the pin using <Pin_x>_Read().


2. If all pins in this same port have power-on reset set to Don't care, the what is the value used?

 

Normally at reset, by default, all pins are configured to analog Hi-Z.  This means that at reset all pins will not be biased to a '0' or '1' state internally.   Depending on how the pin's circuit is configured externally, it might cause a 'glitch' in the pin's value until it gets configured as desired shortly after reset and before main().   You have to determine if this would adversely effect your circuit design.

As a potential 'fix', the "Power-on Reset:" field on the "Reset" tab allows for you to pre-bias the pin at power on reset to either a '0' or a '1'.   By default, the "Power-on Reset:" is set to "Don't Care" which means that the current pin's bias setting is left "as is" and is not changed.   The PSoCs as they come from the factory are set to "Analog Hi-Z".   

However, you can change this setting to specifically bias the pin at reset.

If you set it to "Analog Hi-Z" (which is the factory default), the pin will 'float' at reset potentially causing a 'glitch'.    For example if this output is used to drive the input to a FET, a floating state may turn on or off the FET which might be unacceptable.  The two bias mode below may help to keep the FET 'happy' in the event of a power-up reset, software reset or watchdog reset.

If you set it to "Pulled-Up", the internal pull-up bias resistor (~3K to 8K) will be enabled.  This resistance may be sufficient enough to prevent a glitch.  You need to confirm in your design.

If you set it to "Pulled-Down", the internal pull-down bias resistor (~3K to 8K) will be enabled.  This resistance may be sufficient enough to prevent a glitch.  You need to confirm in your design.

Note:  The non-volatile latch that stores this value internally has a limited write endurance cycle.  Therefore it is cautioned to prevent over use of this feature.  This is especially true on PSoCs used as parts during the development cycle.   Overuse may result in the part not maintaining its desired power reset state,

Len
"Engineering is an Art. The Art of Compromise."
yaga_3967241
Level 3
Level 3
50 sign-ins 25 sign-ins 10 replies posted

Hi Len,

Thanks for your quick and detail replies. In our case, we don't have output and HW connection selected. As in below screenshot. In this case, is the Strong drive mode bypassed completely?

yaga_3967241_0-1681490233774.png

Regards,

Winston

 

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Winston,

Since "Digital Output" is not selected "Drive mode" does not apply.  In theory, based on good GUI practices, the field should be ghosted out.    ANY changes to "Drive mode" and "Initial Drive State:" are ignored.

As to your question 2):  The POR setting in the "Reset" tab might still be useful to bias the input depending on your circuit needs.

Len
"Engineering is an Art. The Art of Compromise."
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