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Hi there, 




I got problem with interfacing Cypress SPI Master running on PSOC 5 Cortex-M3 MCU with Avalon-ST SPI Core running on MAX 10 FPGA Altera. 




Any Suggests, 

1 Reply
Level 10
Level 10
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Welcome in the forum.


A bit bare information to make suggestions. Can you please post your complete project so that we all can have a look at all of your settings. To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file.