Instantiate a clock inside a verilog component

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
HuEl_264296
Level 5
Level 5
First like given 25 sign-ins First solution authored

I am creating a Verilog component which requires a clock. I would like this to be an internal clock, so that the user doesn't need to concern themselves with it.

   

 

   

I have seen some components (eg PWM) which have the option of an internal clock. This is implemented by using a schematic component containing the clock plus another verilog component.

   

 

   

Is it possible instead to simply instantiate a clock within the Verilog?

0 Likes
2 Replies