Jun 14, 2013
11:57 AM
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Jun 14, 2013
11:57 AM
I am creating a Verilog component which requires a clock. I would like this to be an internal clock, so that the user doesn't need to concern themselves with it.
I have seen some components (eg PWM) which have the option of an internal clock. This is implemented by using a schematic component containing the clock plus another verilog component.
Is it possible instead to simply instantiate a clock within the Verilog?
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PSoC 3
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