I2C DMA setup to SRAM

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JiAs_1343366
Level 3
Level 3
10 replies posted 10 sign-ins 5 questions asked

We are looking for information to code DMA functions to auto transfer data to and from SRAM and I2C Master and slave.

We were able to fit 3ea I2C Slaves and 3 I2C Masters along with 6 DMA modules into the CY8C5888LTI-LP097.

We need to setup the DMA channels to operate automatically and continuously to duplicate SRAM data from one 5888 to another 5888.
The data is 8-bits and we have 16 bytes to transfer. The number of SRAM to duplicate between MPU's may grow as the project grows.

I do not expect someone to code for us, just supply help understanding the DMA setup.

The datasheet is not clear or as clear as it could be.

Thank you for your assistance!

 

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MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Hi,

The timing warnings for the I2C seem to be the accuracy realated,

as usual IMO has +/- 5% accuracy which seem to be not good enough.

For a PSoC 5LP, we can fool the system that we will use USB,

then we can have IMO with +/- 0.25% 

001-Configure_System_Clocks.JPG

With this setting warnings of clock accuracy seemed to be fixed.

Then about SPISx_CLK Asycnchronous path(s)...
OH, here is the "Warning-1350" !

OK, it says "asynchronous path", I put dffs to sync sclk to the bus clock

002-SPI_SLAVE.JPG

And there were no more warnings.

moto

Edited: The clock name in the schematic was wrong, corrected with the archive.

 

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JiAs_1343366
Level 3
Level 3
10 replies posted 10 sign-ins 5 questions asked

We are receiving 15 timing warnings.

I archived the project without any of our confidential code.

We were not sure if we needed to include the interrupt connections in the I2C modules.

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MotooTanaka
Level 9
Level 9
Distributor - Marubun (Japan)
First comment on blog Beta tester First comment on KBA

Hi,

The timing warnings for the I2C seem to be the accuracy realated,

as usual IMO has +/- 5% accuracy which seem to be not good enough.

For a PSoC 5LP, we can fool the system that we will use USB,

then we can have IMO with +/- 0.25% 

001-Configure_System_Clocks.JPG

With this setting warnings of clock accuracy seemed to be fixed.

Then about SPISx_CLK Asycnchronous path(s)...
OH, here is the "Warning-1350" !

OK, it says "asynchronous path", I put dffs to sync sclk to the bus clock

002-SPI_SLAVE.JPG

And there were no more warnings.

moto

Edited: The clock name in the schematic was wrong, corrected with the archive.

 

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