I know I'm trying to pack 10lbs in a 5lb bag...
I have a delsig/sar/my own verilog code/several timers/ an I2C master in UDB/ an i2c slave in FF/ and a bunch of other random bits and pieces.
I am nearly finished adding all the features to the project but just as I'm adding the last few equations to the verilog code, I've come up against:
E2071: The design requires 26 UDB(s) but the device has 24. See the report file for details.
------------------------------------------------------------
Technology mapping summary
------------------------------------------------------------
Resource Type : Used : Free : Max : % Used
============================================================
Digital clock dividers : 4 : 4 : 8 : 50.00%
Analog clock dividers : 2 : 2 : 4 : 50.00%
Pins : 46 : 26 : 72 : 63.89%
UDB Macrocells : 155 : 37 : 192 : 80.73%
UDB Unique Pterms : 334 : 50 : 384 : 86.98%
UDB Total Pterms : 352 : : :
UDB Datapath Cells : 15 : 9 : 24 : 62.50%
UDB Status Cells : 12 : 12 : 24 : 50.00%
Status Registers : 3
StatusI Registers : 9
UDB Control Cells : 5 : 19 : 24 : 20.83%
Control Registers : 4
Count7 Cells : 1
DMA Channels : 0 : 24 : 24 : 0.00%
Interrupts : 4 : 28 : 32 : 12.50%
DSM Fixed Blocks : 1 : 0 : 1 : 100.00%
VIDAC Fixed Blocks : 0 : 4 : 4 : 0.00%
SC Fixed Blocks : 0 : 4 : 4 : 0.00%
Comparator Fixed Blocks : 0 : 4 : 4 : 0.00%
Opamp Fixed Blocks : 0 : 4 : 4 : 0.00%
CapSense Buffers : 0 : 2 : 2 : 0.00%
CAN Fixed Blocks : 0 : 1 : 1 : 0.00%
Decimator Fixed Blocks : 1 : 0 : 1 : 100.00%
I2C Fixed Blocks : 1 : 0 : 1 : 100.00%
Timer Fixed Blocks : 0 : 4 : 4 : 0.00%
DFB Fixed Blocks : 0 : 1 : 1 : 0.00%
USB Fixed Blocks : 0 : 1 : 1 : 0.00%
LCD Fixed Blocks : 0 : 1 : 1 : 0.00%
EMIF Fixed Blocks : 0 : 1 : 1 : 0.00%
LPF Fixed Blocks : 0 : 2 : 2 : 0.00%
SAR Fixed Blocks : 1 : 1 : 2 : 50.00%
The Technology Mapping section - Design Equations has lots of details in it:
MacroCell: Name=Net_1267, Mode=(Combinatorial)
Total # of inputs : 4
Total # of product terms : 2
Clock Enable: True
Main Equation : 2 pterms
(
Net_1740_5 * \I2CEngine:go_run\ * !\I2CEngine:bit_phase_q_1\ *
debug_1
+ Net_1740_5 * \I2CEngine:go_run\ * \I2CEngine:bit_phase_q_1\ *
!debug_1
);
Output = Net_1267 (fanout=1)
But how can I figure out who is really sucking up all the resources?
If each block in the schematic had a corresponding MC count or something that would clue me in. I tried commenting out a few things in the verilog file which made some logic go away but I get very inconsistent results. If I add 1 OR in 1 equation I go from fitting to missing by 2 UDBs, then add another equation and then it fits again???
There are various features I can probably live without but it I'm not sure which one will give me back the most UDBs. I also know that routing is often the real issue and I'm not really out of UDBs but interconnect wires. Is there a report for that somewhere?
I have learned a few things along the way:
in Verilog code:
1) NEVER build arithmetic devices in verilog. Use a schematic. Verilog turns into AND/OR terms and quickly explodes UDB count. In schematics, they use data-path cells which there are plenty of. So counters, adders and anything arithmetic do them via schematic. Verilog code should be just control.
Well maybe I only learned 1 thing so far... Can't think of anything else right now - I should have written more down as I was going...
