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PSoC™ 5, 3 & 1 Forum Discussions

RaAl_264636
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Hi,

according to the 5LP reference manual the datapath outputs are registered, but it's also possible to use the combinational signal. Unfortunately, I can't find any information about how to enable the combinational output on the device.
For simulating the component, I figured out that it seems to be enough to override a parameter, e.g. so_sync, etc.

But I doubt that this is the correct way to enable combinational output on the PSoC device. Digging deeper into the device manuals shows that this feature seems to be bound to the corresponding UDB config register #8. The default value of this register within the component definition is 0x00.
But here the user can't know which bit is assigned to the output which should be combinational. So, how to correctly enable combinational output for datapath output mux?

Regards

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Ekta
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Hi @RaAl_264636 

From the description of your issue, it seems that you are trying to create a component that uses combinational logic. Can you please clarify if this is the case?

If yes, please refer to the PSoC Creator UDB Editor Guide which mentions how you can create a component using Verilog and UDB Editor tool. When using Verilog to create any component it is possible to write the code in such a way that the output is combinational.  You are allowed to use other legal Verilog combinational logic statements, such as A&B (if A and B were variables in your design).

You can refer to the PSoC Creator - Implementing Programmable Logic Designs with Verilog to understand how a component can be created in PSoC using Verilog.

The attached documents might also be helpful. Kindly let me know if my understanding of the issue is not correct.

Thanks 
Ekta

 

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RaAl_264636
Level 5
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Hello @Ekta 

yes, I think(!) I need the combinational output, but not from a verilog-only component. I need it from datapath. The reference manual states that it's possible to have combinational datapath output, but it doesn't state how to achieve it.
So the question is how to enable the combinational datapath output.

Regards

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Len_CONSULTRON
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RaAl,

I don't know if this is helpful:

In the "Just Enough Verilog for PSoC (2).pdf"  there is a reference to constructing combinatorial logic in Verilog.

Len_CONSULTRON_0-1655392092300.png

However, what Infineon needs to answer is whether a datapath output follow these rules.

 

Len
"Engineering is an Art. The Art of Compromise."
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RaAl_264636
Level 5
25 sign-ins 10 solutions authored 250 replies posted
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Hello @Len_CONSULTRON 

as far as I understood combinatorial logic is made of either logic equations/assignment or with an always block where the sensitivity list doesn't contain an edge triggered signal. Sequential logic is always triggered on a rising/falling edge event (keywords posedge/negedge for the sensitivity list).
According to the documentation, the datapath output can be combinational, but as I wrote it's not documented.

The files provided for datapath simulation can be switched to combinational output by parameter, see lines 117-132 of cy_psoc3_dp.v file. So I created a small test simulation for this and the result showed a difference in the output.
Then I tried the same on the PSoC device and it seems that the parameter is also accepted. Provided that my test firmware for the PSoC device works correctly, the result also shows the different behaviour. So, it seems it's pretty easy to switch from registered to combinational output by simply overriding the corresponding sync parameter value with 1'b0. @Ekta can you confirm this?

Regards

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RaAl_264636
Level 5
25 sign-ins 10 solutions authored 250 replies posted
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Hello@Ekta 

I'd really appreciate if you can give an answer about my observations.

Regards

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Ekta
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Hello @RaAl_264636 

Can you please share which lines you are referring to in the verilog file? I am aware that for every UDB component you create there can be a corresponding Verilog file. But I am unable to find the cy_psoc3_dp.v file. 

I went through the Designing PSoC Creator Components with UDB Datapaths Guide
and I could find that the datapath configuration tool has an add sync parameter that – Determines whether an additional sync flip-flop is added to the FIFO block status. This controls the cycle timing between bus reads/writes at bus clock resolution, and the assertion of the new status on datapath output routing. There is only one configuration bit that controls this for both FIFOs. Please refer to the image attached:

Ekta_0-1657023695156.png

Best Regards
Ekta

 

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RaAl_264636
Level 5
25 sign-ins 10 solutions authored 250 replies posted
Level 5

Hello @Ekta 

as I wrote I'm referring to the lines 117-132 in cy_psoc3_dp.v file which can be found in "C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\sim\presynth\vlg" folder

You won't find anything about this feature in AN82156, it's mentioned in the architecture reference manual 78426, rev G, page 169:

RaAl_264636_0-1657039405382.png

But it's not stated how to do it. As I wrote above, according to register manual it seems to be tied to UDB register #8:

RaAl_264636_1-1657039607059.png


But there's also a parameter in the mentioned cy_psoc3_dp.v file. I used this parameter during simulation and also for the real component and it looks like the parameter is also accepted for the real component. I'm looking for a confirmation that it's enough to use the parameter and that the UDB register #8 does nothing. If this register has any function, I'd be glad to know what it does.

Regards

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