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PSoC™ 5, 3 & 1 Forum Discussions

DaGr_294516
Level 2
Level 2
First solution authored 5 sign-ins 10 replies posted

How long would a voltage have to be below the detection threshold to trigger an interrupt?

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6 Replies
Len_CONSULTRON
Level 9
Level 9
500 solutions authored 1000 replies posted 750 replies posted

DaGr,

I assume this is what you are looking for.

Len_CONSULTRON_0-1671366740636.png

This is found in the PSoC5LP datasheet.

Len
"Engineering is an Art. The Art of Compromise."
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Is that the time taken for the LVI monitor to respond to the event, or the duration of an event which would be neeeded to trigger the monitor? The latter is what i'm interested in.

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DaGr,

This would be the maximum time to initiate a LV ISR event.

How much time it takes for you execute a mitigation strategy (write to registers, turn off/on power consuming peripherals, go to sleep, write to EEPROM ...) is up to you.

Len
"Engineering is an Art. The Art of Compromise."
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Sorry if this is already what you mean but i need to be 100% clear. By maximium time, do you mean the time for which the voltage being monitoted has to be below the threshold for it to be considered an event?

The time to respond to the event  is much less important to me, i'm trying to track very brief drops, that's the problem.

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DaGr,

I'm not an Infineon employee so I don't have access to the internal structure of the LVI HW. 

At best I can imagine some some propagation delay from comparator being used to watch for the LVI and prop delay in the interrupt resolution hardware that finds the interrupt vector to use.

Maybe someone from Infineon can be more instructive here.

I don't know your LVI requirements but I have three suggestions that you probably already considered.

  1. Use a higher LVI threshold to trigger for advanced warning to mitigate or warn.
  2. Make you HW more robust.
  3. You can have a multi-threshold scheme that does scaled mitigation.  At the higher threshold, you can turn off some higher consuming peripherals.  At the next lower, you can write to EEPROM.  And so on ...
Len
"Engineering is an Art. The Art of Compromise."
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Thanks for the suggestions, 2 is probably where we'll be focusing for now.

In case anyone from Infineon does see this, the exact number i'm after is td on the timing diagram below.

DaGr_294516_1-1671448154535.png

Let's say te is the length of a low voltage event, td is the time taken for the LVI hardware to detect the event and ti the time after detection an interrupt will actually occur. For an intterupt to occur, it must be true that te > td. I'm interested in the value of tdnamely the shortest value of te for which an interrupt would occur.

I think having had further look, the original number you pointed to in the datasheet probably was the answer I was looking for. The reason for my confusion is that i think "response time" is ambigous, and could refer to td, ti or  td + ti.

In the PSoC 4 datasheet the same value of 1uS is given for Tmontrip or the "voltage monitor trip time" which makes me think it is td after all. If anyone could confirm this that would be great 🙂

DaGr_294516_0-1671447912537.png

Cheers again for your help.

Dan

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