How do I read/understand UDB "Basic" Components in CyComponentLibrary?

[BuHa_1507271]

I've been reading through the CyComponentLibrary sources installed with PsocCreator.   Many of the components, like the shift register, are apparently composed of a low level component (e.g. BShiftReg_v2_30.v), and a higher-level component (e.g. ShiftRegister_v2_30.cysch.)   While the higher-level component can be read in the PsocCreator schematic editor, the real guts of this component are in the Verilog file for the low-level component which is implemented (mostly) in a datapath.

Is there any way of examining a low-level component file like BShiftReg_v2_30.v at a higher level than the Verilog text, i.e. the sort of diagram produced by PsocCreator when I choose to make a new UDB document?

[Ekta_N]

Hello BuHa_1507271​

In order to see all the files associated with a UDB component:

1. You can go to the components tab in PSoC Creator Workspace, right click on the project and select Import Component.

2. In the Import Component dialogue box select the following:

Import from Project/Library: CyComponentLibrary

Source component: Select the component you wat to import (Shift_reg or BshiftReg_v2.30 in this case)

After importing the component you should be able to see all the files associated with the component, as shown in the figure below:

"Is there any way of examining a low-level component file like BShiftReg_v2_30.v at a higher level than the Verilog text, i.e. the sort of diagram produced by PsocCreator when I choose to make a new UDB document?"

As far as I know it is not possible to view the component at a higher level than verilog. This is because the UDB based component is created using only verilog code.

In case a component is created using schematic then it is possible to view the schematic file (.cysch) of the component. Both the schematic file and the verilog file can be used to create component symbol file.

Can you please elaborate what exactly do you mean when you say " the sort of diagram produced by PsocCreator when I choose to make a new UDB document"

You can refer to the following appnote for the various methods of creating a UDB based component: https://www.cypress.com/file/41531/download

Best Regards

Ekta

[BuHa_1507271]

Thank you for your reply EktaN.   You said:

> Can you please elaborate what exactly do you mean when you say " the sort of diagram produced by PsocCreator when I choose to make a new UDB document"

Yes, I mean a diagram (or something like it) like this:

Specifically, I'm looking for one corresponding to the part of BShiftReg_v2.30.v saying:

localparam dp8_cfg = {         `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_A0,         `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,         `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,         `CS_CMP_SEL_CFGA, /*CFGRAM0:     IDLE*/         `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_A0,         `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,         `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,         `CS_CMP_SEL_CFGA, /*CFGRAM1:     IDLE*/         `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_A0,         `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,         `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,         `CS_CMP_SEL_CFGA, /*CFGRAM2:     IDLE*/

. . .

But obviously the table is more compact.

[BuHa_1507271 · Accepted solution]

I think I'm on the right track now.   There is something called the The Datapath Configuration Tool which seems to know how to load the .v file and decode the datapath configuration.  I'm no expert, but it looks like this:

[Ekta_N]

Hello,

You are right. The Datapath Configuration Tool is an application that allows you to create, view, modify, and delete datapath instances within Verilog files. The tool parses a Verilog file and displays each datapath as an entity, called a "configuration" in the tool.

You can refer to the Designing PSoC Creator Components with UDB Datapaths document which shows details all the examples using the Datapath Configuration Tool.

Best Regards

Ekta