Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

PSoC™ 5, 3 & 1 Forum Discussions

PaCo_972561
Level 2
5 questions asked 5 replies posted Welcome!
Level 2

Hi - I'm using a WaveDAC8 in my PSoC 5 LP design.  I set the WaveDAC8 clock to 1 MHz and I get a timing violation warning:

Warning: sta.M0019: NORAD_controller_1_timing.html: Warning-1367: Hold time violation found in a path from clock ( CyBUS_CLK ) to clock ( \WaveDAC8_1:Wave1_DMA\/termout ). (File=B:\OpticalDelayLine2018\PSoC_projects\Workspace_NORAD\optical_switch_controller_1\NORAD_controller_1.cydsn\NORAD_controller_1_timing.html)

I tried to lower the WaveDAC8 clock to 500 kHz and got the same warning...

Any suggestions?

thanks much - Paul

0 Likes
1 Solution
odissey1
Level 9
First comment on KBA 1000 replies posted 750 replies posted
Level 9

Paul,

If permitted, please upload a project: (1). Build->Clean; (2) File->Create workspace bundle->Minimal; (3) to reduce file size delete "Generated_source" folder in newly created archive.

I believe that the issue arises due to wc1/wc2 outputs. These are direct output from DMA nrq output, which is not in sync with BUS_CLK. Try to add a Sync component to it, synchronized to the BUS_CLK.

/odissey1

View solution in original post

0 Likes
2 Replies
odissey1
Level 9
First comment on KBA 1000 replies posted 750 replies posted
Level 9

Paul,

If permitted, please upload a project: (1). Build->Clean; (2) File->Create workspace bundle->Minimal; (3) to reduce file size delete "Generated_source" folder in newly created archive.

I believe that the issue arises due to wc1/wc2 outputs. These are direct output from DMA nrq output, which is not in sync with BUS_CLK. Try to add a Sync component to it, synchronized to the BUS_CLK.

/odissey1

0 Likes
PaCo_972561
Level 2
5 questions asked 5 replies posted Welcome!
Level 2

Thanks for the SYNC suggestion on the WC output.  That did the trick, no timing warnings now.  Thanks very much.

Paul

0 Likes