1. Data is placed on Data lines by Host. 2. Host then indicates a Data Cycle will proceed by asserting HostAck. 3. Host indicates valid data by asserting HostClk low. 4. Peripheral sends its acknowledgment of valid data by asserting PeriphAck. 5. Host de-asserts HostClk high. +ve edge used to shift data into the Peripheral. 6. Peripheral sends it's acknowledgment of the byte via de-asserting PeriphAck.
Ok so say I transfer 512 bytes from the PC/Linux to the PSOC3. The problem I see is how do I know when the DMA transfer of each byte is done so I can indicate to the ECP port PeriphAck?
So I use the HostClk to indicate to the DMA that a transfer is required. But when do I know it read the port?
Same true with IDE if DMA or FIFO mode is used, how do I know the DMA read the port?
Or do I have to use the PLD functions to do this, some sort of latching then read?