For ADC SAR component pin POR state and state after bootup

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yaga_3967241
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Hi,

We are using PSoC 5LP and for its ADC SAR component, there is a bypass pin that need to be assigned. What is the power on reset state of this pin? What is the pin's state after PSoC bootup? Seems there is no such things like Drive mode and Initial value for this pin.

 

Regards,

Yan

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Vasanth
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Hi Yan,

PSoC 5 LP have special nonvolatile latch (NVL) bits that can be used to set pin behavior immediately after reset is released. These I/O NVL behavior settings become effective during hardware startup. Pins and other resources begin to behave as desired following a set delay after reset is de-asserted or power supply ramp meets requirements. This delay is specified in the datasheet as “TIO_INIT”. This value is on the order of microseconds. NVL-controlled pin behavior is configured in the pin component customizer. If the NVLs are not configured, the pins remain in the analog High-Z drive mode until they are reconfigured to their run time state. The bypass pin also follows the same .

Best Regards,
Vasanth

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Vasanth
Moderator
Moderator
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250 sign-ins 500 solutions authored First question asked

Hi Yan,

PSoC 5 LP have special nonvolatile latch (NVL) bits that can be used to set pin behavior immediately after reset is released. These I/O NVL behavior settings become effective during hardware startup. Pins and other resources begin to behave as desired following a set delay after reset is de-asserted or power supply ramp meets requirements. This delay is specified in the datasheet as “TIO_INIT”. This value is on the order of microseconds. NVL-controlled pin behavior is configured in the pin component customizer. If the NVLs are not configured, the pins remain in the analog High-Z drive mode until they are reconfigured to their run time state. The bypass pin also follows the same .

Best Regards,
Vasanth