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Greetings, I have a question related to PSoC5LP:
I'm using an ADC DelSig, DMA, Filter and VDAC, pretty much like the Filter_ADC_VDAC example. The ADC resolution I'm using is 16-bit with a 48 ksps conversion rate, same rate for the filter.
After the filter interrupt, I need to change the sampling rate from 48 kHz to 20*48 kHz = 960 kHz and have this associated to another interrupt where I can process the sample that comes from the filter interrupt.
For instances, the value that comes out of the filter's interrupt should go directly to this new interrupt, hold it and process the same sample 20 times with a 960 kHz sampling frequency, then, write it into the VDAC (after shifting from 16 to 8 bits).
Is the Sample & Hold component ideal for this situation or a clock connected to an interrupt should work? What's the best way to implement it, considering this case? Thanks for your time and help!
Solved! Go to Solution.
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ja.duarte,
Attached below is upsamping demo using second-order hardware LPFilter component. Tested both in 16-bit and 8-bit versions with no noticeable differences in the output. In 8-bit mode, only 23% of PLD space is used. The FFT shows almost 50db suppression of the 48Hz (sampling) and 960kHz (interpolated) frequencies. The second harmonic of the 3kHz sine signal is only 40db suppressed, which indicates shape asymmetry, which seems to come from original input signal ditortion.
To replace WaveGen_A with DelSig_ADC: (1) delete WaveGen_A from schematic; (2) Copy-paste ADC and DMA from your original project.
/odissey1
Fig. 1. Second-order h/w interpolator. VDAC_A - straight Filter output, VDAC_1 - interpolated.
Fig. 2. FFT of the interpolated output. Yellow trace - Filter output, Fuchsia - interpolated.
Fig. 3. FFT of (non-interpolated) Filter output. Yellow trace - Filter output, Fuchsia - interpolated.
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ja.duarte,
To better assist you, please describe what is the goal of the project, why 20x rate multiplier is needed and what kind of processing is planned in 960kHz interrupt.
/odissey1
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user_342122993,
The goal is to implement a Delta-Sigma modulator DAC capable of interpolating 20 samples between the sample n and n-1 that comes from the Filter.
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ja.duarte,
One way of 20x interpolating is to use the Filter itself. Basically, the data income rate to the Filter should be 960 kHz (20x48kHz), so that Filter will smooth transition between actual data points. To achieve this, DMA should be operating at 20x clock the ADC does, so it will pump same data 20 times from ADC holding register. The smoothed output from Filter will be at 960kHz rate, which can go to VDAC directly (no ISR is necessary).
For example:
ADC output: 0
Filter input: 0,0,0,0,0.... (20 times)
ADC output: 20
Filter input: 20,20,20,20,20,... (20 times)
etc.
...
Filter output (sort of):
1,2,3,4,5,6... etc.
Secondly, the Filter input clock does not have to be exactly 20x of ADC (Filter has no clue about actual time, any incoming data considered equally spaced). So the data can be fed into Filter at max rate possible, and output is buffered in RAM. Then VDAC will oputput data from RAM at 960kHz rate by DMA.
/odissey1
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I'm using both channels of the filter. So basically, I'm using the filter's interrupt to filter what comes from the ADC with channel A, then I have some math to do over each sample (applying a distortion function), and after this I apply the channel B filter. I only want to start the interpolation after filtering with channel B and then, send it to the VDAC.
This should emulate the characteristics of a guitar amplifier. I should have been more specific about the whole project, sorry.
How can I do all of these maths on the right sampling frequency without interrupts? Also, I have to do some math regarding the delta-sigma modulator, so that's why I thought two interrupts should be needed for both sampling rates.
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How can I change DMA to operate at 20x clock the ADC does? Thanks a lot for your help!
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ja.duarte,
Attached is example of data interpolation on the output from the Filter. It is sensitive to processor load and may need more testing and optimization. It uses DMA buffer size of 40, divided by 2 halves (20+20). When Filter data is available, the expired half-buffer is filled with interpolated values, while outputting data from the other half-buffer. Instead of DelSig-ADC, a WaveGen8 custom component is used for testing to avoid using external signal generator. It is unpublished custom component, which encapsulates RAM buffer and DMA channel to feed various targets with 8-bit data.
I believe that you already have DelSig_ADC-Filter section working, and can replace WaveGen_A with DelSig_ADC without a problem. The Filter output can be polled or read on interrupt (default), there is subtle difference in performance due to timing synchronization. Here a simple linear interpolation is used to fill the gap, but other smoothing algorithms can be used as well. Timing seems to be important, the Release option works more stable than Debug. Let me know it this works for you.
WaveGen8 component is included into the project and provided as-is. The Annotation library for KIT-059 can be found here:
Annotation library for CY8CKIT-059 Prototyping Kit
/odissey1
Fig. 1. Linear 20x s/w interpolator (upsampler). VDAC_A - straight Filter output, VDAC_1 - interpolated.
Fig. 2. FFT of the linearly interpolated output. Yellow trace - Filter output, Fuchsia - interpolated.
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ja.duarte,
Attached is another approach (hardware) approach to Filter output stream interpolation. This time, 1-st order low-pass filter is used for inerpolation of the incoming data. On Filter interrupt, the data is copied to wide Control Register (CReg32 component), which feeds LPFilter input bus. The LPFiter dumping width is set to 4 (dumping length = 2^4 = 16), which is comparable to interpolation scale (x20).
The WaveGen8, ControlRegister32 and LPFilter are unpublished custom components; they are imported directly into the project for easy start. The Annotation library can be downloaded elsewhere:
Annotation library for CY8CKIT-059 Prototyping Kit
The difference between two projects is interpolation algorithm, performance and resources consumption. Due to h/w implementation, the LPFilter allows for very high input/output frequency (12-14 MHz is OK) without CPU load, but shows some exponential curvature between the points. Changing LPFilter dumping width to 5 improves this curvature in expense of some loss in amplitude. The LPFilters can be cascaded, creating 2-nd, 3-rd, etc. order filter. To save h/w resources, use less bits from the filter e.g. 8 or 12 - afterwards, the output of VDAC is only 8-bits anyway!
/odissey1
Fig. 1. First-order h/w interpolator. VDAC_A - straight Filter output, VDAC_1 - interpolated.
Fig.3. FFT of the interpolated Filter output. Yellow trace - Filter straight output, Fuchsia - interpolated output.
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ja.duarte,
Attached below is upsamping demo using second-order hardware LPFilter component. Tested both in 16-bit and 8-bit versions with no noticeable differences in the output. In 8-bit mode, only 23% of PLD space is used. The FFT shows almost 50db suppression of the 48Hz (sampling) and 960kHz (interpolated) frequencies. The second harmonic of the 3kHz sine signal is only 40db suppressed, which indicates shape asymmetry, which seems to come from original input signal ditortion.
To replace WaveGen_A with DelSig_ADC: (1) delete WaveGen_A from schematic; (2) Copy-paste ADC and DMA from your original project.
/odissey1
Fig. 1. Second-order h/w interpolator. VDAC_A - straight Filter output, VDAC_1 - interpolated.
Fig. 2. FFT of the interpolated output. Yellow trace - Filter output, Fuchsia - interpolated.
Fig. 3. FFT of (non-interpolated) Filter output. Yellow trace - Filter output, Fuchsia - interpolated.
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Sorry for the late reply /odissey1. I was out of town for a week, just came back. I was trying this last implementation you suggested me but these errors keep popping up and I have no idea how to solve them:
ADD: fit.M0002: error: Can't find 'LPFilter' in library 'work' with path 'lcpsoc3'.
ADD: fit.M0002: error: Can't find 'ControlReg32' in library 'work' with path 'lcpsoc3'.
Do you have any idea how can I solve this??
Thank you!
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ja.duarte,
What Creator version you using?
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PSoC Creator 4.2 (4.2.0.641)
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ja.duarte,
I downloaded
WaveGen_Filter_LPFilter2_01a_upload-000.cywrk.Archive01.zip
unzipped, and opened *.cyprj file using Creator 4.2. There were 8 errors, which all come from KIT-059 annotation library kit, which can be downloaded here:
Annotation library for CY8CKIT-059 Prototyping Kit
Alternatively, the annotation components can be safely deleted without affecting project performance.
Other than this, everything works fine. Please let me know if the issue resolved.
/odissey1
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ja.duarte,
Attached is useful paper from Agilent on data upsampling/interpolation. Original article can be found here:
A proper way to implement Sin(x/x interpolation would be using the Filter component with custom coefficients, but that would require to re-design original project.
/odissey1
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Thank you /odissey1, the interpolation is now working on my project! Although, I still have to implement the Delta-Sigma modulator under 960 kHz with some code and I think that I'm only working under 960 kHz by the time I write into the ControlReg32.
I would like to implement something like this but with the correct clock.
int main(void)
{
Init();
for(;;)
{
if (flag_DtrReady)
{
flag_DtrReady=0;
Filter_Result = 128u + Filter_1_Read8(Filter_1_CHANNEL_A);
//2nd order DelSig Modulator with 8-bit quantification CODE under 960 kHz
//...
//...
modulator_out = //code.......
CReg32_1_Write(modulator_out);
}
}
Thank you once again!
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ja.duarte,
I don't understand what you a trying to achieve with this DelSig modulator staff, and why it needs data input at 960kHz rate? Do you want convert analog wave into digital 1-bit stream, operating at 960kHz frequency?
as to the code snippet below, the flag_DtrReady being fired at sample rate of 48kHz. Then LPFilter reads CReg32 at 960kHz, multiplying stream rate 20x times.
if (flag_DtrReady)
{
flag_DtrReady=0;
Filter_Result = 128u + Filter_1_Read8(Filter_1_CHANNEL_A);
/odissey1
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With the DelSig modulator I can reach a SNR over 90 dB and will end up with a better quality DAC.
This is the way I'm implementing it on Matlab. Consider an input x with 16 bit values:
The code snippet in MATLAB implements a 3rd ordem Sigma Delta Modulator:
Vref = 256;
nbitsq=8;
y(i)=round(x(i-1)/2^nbitsq);
e(i)=y(i)*Vref - x(i-1);
x(i)=vin(i) - (3*e(i) - 3*e(i-1) + e(i-2));
vin is the value that comes from the filter at 48 kHz.
With this, I will end up with an output y quantized for 8 bits, but this should be processed under 960 kHz so I can process each value that comes from the ADC 20 times... and then I could actually integrate this with your interpolation method.
Here's a Matlab plot comparing the DAC with and without the modulator.
Sorry if this sounds confusing and thanks a lot for your help.
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ja.duarte,
this is interesting staff, which I am not familiar with. Do you have any links with more info on DelSig modulator?
/odissey1
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This is another approach for data interpolation (upsampling), which potentially can be done in PSoC5 hardware:
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/odissey1, sorry for the huge delay.
Thanks a lot for the help and for all the tips! I have no documentation regarding DelSig modulator. I asked my advisor if he could send me some, but he also has to search for it. I can still send you the Matlab code I'm using. I think it's pretty easy to understand.
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ja.duarte,
I learned a bit about upsampling and Del-Sig modulator since last time, and believe they are different things. The upsampling is a process of staffing more data points between original data. For example, 20x upsampling of 48kHz, results in 960kHz output update rate. This doesn't improve VDAC resolution. PSoC5 has 8-bit VDAC only, so no matter what, the THD will be no better than ~48dB.
Another thing is improving VDAC resolution (e.g from 8-bit to 16-bit). Here Delta-Sigma modulator can help (theoretically). Basically, instead of writing VDAC output register value N, we update it between N-1, N and N+1 at high speed (as controlled by the D-S modulator). The time-averaged VDAC output will be of higher resolution. In practice this doesn't work that well, because of 8-bit VDAC hardware imperfections INL/DNL). Previous experiments using PSoC5 showed that 9-10-bits is the the practical limit for a slow signals. With high-speed signals (~1MHz), situation is much worse as PSoC5 VDAC certified only to about 100kHz. Above this threshold, VDAC starts showing bit-flipping glitches (xxx1 0000 <-> 0000 1111), and actual resolution decreases.
I drafted some Verilog code for 2-nd order Delta-Sigma modulator, but not tested it with VDAC yet. Keep in mind that to achieve higher resolution, the VDAC update rate form the Modulator must be likely 20-200x faster than desired output rate. If after interpolator it was 960kHz, now it needs approx 20-200MHz, which is not feasible with PSoC5 VDAC hardware.
I have no idea what is going to happen if both upsampling and Delta-Sigma frequencies made to coincide. To be honest, I don't know how to measure 90dB THD using a standard 8-bit scope.
Hope that somehow clarifies the problem.
/odissey1
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Do you know if those bit-flipping glitches occur in frequencies above 20 kHz? Because this is for an audio device, so if those glitches are not present in between the audio spectra, it won't cause any trouble to me.
Do you think you can provide that Verilog code for the 2nd order Delta-Sigma?
Thank you!
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ja.duarte,
I will provide Delta-Sigma modulator demo over weekends. It is still "in progress".
PSoC5 VDAC8 bit-flipping demo screenshot is provided below. For full sine (0-255) is gives 16 glithes per period. If VDAC sampling rate >1MHz, a LP filter is necessary. This is hardware issue specific to PSoC5, for example PSoC4 (IDAC8) has almost no glitches.
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ja.duarte,
Attached is DelSig Modulator example project, which includes both 1-st order and 2-nd order modulator examples on separate pages. Disable current page before switching to another one to avoid error messages. The 1-st order modulator seems to work OK. The 2-nd order modulator needs more testing. To tune VDAC output, a shaft rotary encoder was used, the Encoder library can be found here:
Quad Decoder with Button Switch component for rotary shaft encoders
Another custom library was used for annotation:
Annotation library for CY8CKIT-059 Prototyping Kit
The DSM component provided as-is, more testing and verification required. The output of the DSM can be routed to VDAC by the bus or DMA. The modulator has 8 fixed and 14 fractional bits (22-bit total), which is overkill for the 8-bit DAC, it can be simplified further to save PLD resources. It is unlikely to obtain better than 10-11 bits from VDAC8 anyways.
/odissey1
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Here is an article which, I believe, describes the intended target design. Not sure if it is doable in PSoC though: