Fast mode Comparator emits multiple pulses

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KaAs_973901
Level 2
Level 2

Hello, I have a circuit that decodes a signal using a parallel RC circuit and a comparator. When the voltage on C1 drops below Vref, Pin_2_4 is sampled and the comparator output is used to clock the shift register.

Unfortunately, when operating in fast mode, the comparator emits multiple pulses and clocks the shift register beyond the single pulse required. When set to 'slow' the comparator behaves (or to a much slower clock speed), however this results in a significantly larger pulse, up to 2uS in width.

I'm seeking clarification on what can be done to operate the comparator in this model and receive only the single desired short pulse, a well as understanding why the faster clock rate and 'fast' mode result in this behavior.

I have also attempted to enable and disable hysteresis with no change in behavior.

Signal captures and a sample project are both attached for clarity.

Thanks,

Karl

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Karl,

Generally I try to stay away from using R,  C  or L s as timing references unless absolutely necessary.

I still don't understand the need for the RC circuit.  Can't it be done with a timer that uses a very good clock source as the input clock?

A word to the wise:  Avoid using analog components in a timing chain unless you expect one of the values of the analog components to change during operation and this is a crucial factor in the application.  A good example of analog components in a timing chain is the cap sensor.  It depends on external capacitance change to increase or decrease the timing.

I fully understand the desire to minimize SW intervention.  I always try to use HW state machines to minimize the CPU and boost performance and reliability.

From your TopDesign and your description above, the EdgeDetect1 is used to start the SR reg and the timing for the FET/RC/Comparator chain.  This in turn produces a delayed clock pulse for the clock input of the ShiftReg.

Let me propose a change to your circuit in TopDesign.  This uses only digital elements in the timing delay for the ShiftReg clock.  It also removes the need for the R and C as external connections.

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This change replaces your RC, SR, and Comparator and NOT gate with a 16bit Fixed function Counter.  The tc output of the counter will provide a rising edge for the shift reg input clock when the count gets to period count value.  Since your R (=12K) and C (=3nF) your RC value is 36 usecs.  With an input clock to the counter of 24MHz,  you need about a period count of 864 to achieve a 36 usec delay from the first edge of the EdgeDetect1 output.  You can more accurately control the delay (with IMO = 3MHz: better than +/- 1%).  Additionally you can 'tune' the delay value without having to change R or C.

Len

Len
"Engineering is an Art. The Art of Compromise."

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