EZI2C - How to identify the list of registers that have been written to or read by Master?

[ShAm_4016726]

Hi,

I am using EZI2C Slave Component.

I would like to know how I can get the list of registers that have been read or written to by host since the last call to EZI2C_GetActivity();

Or any other suggested way to get this information. Note that my application requires to know both the read and written to registers to act on them.

I have followed through with the suggestion of reading the EZI2C variables directly in EZI2C_ISR_ExitCallback for

EZI2C_rwOffsetS1; and EZI2C_isr_call_data[lc].index = EZI2C_rwIndexS1;

but I don't get a consistent indication of the read or write.

I have followed some recommendation from the following post PSoC 5LP EZI2C Write  but I have not been able to get the read and written to registers identified to act on this.

Any help, specially, if there is code example, that would be very helpfull.

Here is additional info if needed:

I am reading "EZI2C_1_curStatus" directly in the Exit ISR and trying to figure out which registers have been touched (read or written to).

    while reg ++ != end

    {

        // has any bytes of the register touched?

        if ( reg >= EZI2C_1_rwOffsetS1)

        {

            if ((reg <= EZI2C_1_rwIndexS1)

            {

                if (temp & EZI2C_1_STATUS_READ1)

                {

                    myregStatus |=  EZI2C_1_STATUS_READ1;

                }

                if (temp & EZI2C_1_STATUS_WRITE1)

                {

                    myregStatus |=  EZI2C_1_STATUS_WRITE1;

                }

            }

The EZI2C_currStatus has values as but most of the time, I get EZI2C_1_STATUS_WR1BUSY  and note EZI2C_1_STATUS_READ1 or EZI2C_1_STATUS_WRITE1

/* Status bit definition */

#define EZI2C_1_STATUS_READ1   (0x01u) /* A read addr 1 operation occurred since last status check */

#define EZI2C_1_STATUS_WRITE1  (0x02u) /* A Write addr 1 operation occurred since last status check */

#define EZI2C_1_STATUS_READ2   (0x04u) /* A read addr 2 operation occurred since last status check */

#define EZI2C_1_STATUS_WRITE2  (0x08u) /* A Write addr 2 operation occurred since last status check */

#define EZI2C_1_STATUS_BUSY    (0x10u) /* A start has occurred, but a Stop has not been detected */

#define EZI2C_1_STATUS_RD1BUSY (0x11u) /* Addr 1 read busy  */

#define EZI2C_1_STATUS_WR1BUSY (0x12u) /* Addr 1 write busy */

#define EZI2C_1_STATUS_RD2BUSY (0x14u) /* Addr 2 read busy  */

#define EZI2C_1_STATUS_WR2BUSY (0x18u) /* Addr 2 write busy */

#define EZI2C_1_STATUS_MASK    (0x1Fu) /* Mask for status bits */

#define EZI2C_1_STATUS_ERR     (0x80u) /* An Error occurred since last read */

[Len_CONSULTRON]

ShAm,

I've never worked with the EZI2C component but I'll give it a try.

Your code fragments above are not quite complete.  Therefore I'm making certain guesses.

The EZI2C_GetActivity(void) API call has this note:

The Read and Write busy flags are cleared when read, but the “BUSY” flag is only cleared when slave is free (that is, the master finishes communication with the slave generating Stop or repeated Start condition).

Len

[BragadeeshV]

Hi ShAm_4016726​,

You can use the following snippet to achieve this:

        if(EZI2C_EzI2CGetActivity() == EZI2C_EZI2C_STATUS_WRITE1)
        {
            EZI2C_DisableInt();
            offset_address = EZI2C_offsetBuf1;
            index_pos = EZI2C_indexBuf1;
            EZI2C_EnableInt();
            numOfBytes = index_pos - offset_address;
       }

EZI2C_offsetBuf1 -> Offset of the register written

Index Position -> Position of the last written byte

Regards,

Bragadeesh

[ShAm_4016726]

Hi Bragadeesh,

I added your suggested code to EZI2C_1_ISR_ExitCallback but I did not get any EZI2C_1_STATUS_WRITE1 at all.

So, the suggested code did not work when added in the EZI2C_1_ISR_ExitCallback .

Note that I need to know all writes between activity call. So, I believe for this it is required to handle it in the ISR_ExitCallback call.

This is the exact code:

void EZI2C_1_ISR_ExitCallback()

{

    uint8 idx;

    uint8 offset_address, index_pos, numOfBytes;

    if(EZI2C_1_GetActivity() == EZI2C_1_STATUS_WRITE1)

    {

        EZI2C_1_DisableInt();

        offset_address = EZI2C_1_rwOffsetS1;

        index_pos = EZI2C_1_rwIndexS1;

        EZI2C_1_EnableInt();

        numOfBytes = index_pos - offset_address;

    }

    return;

}

I have got my code (the following code)working and I can get all the read and writes that are taking place. This code is the following exact code.

The key code was checking for STOP bit Status.

I still did not get the READ1 and WRITE1 but ended up using RD1BUSY and WR1BUSY. Given that the STOP has been detected, I converted this to READ1 and WRITE1 as below.

Please ignore my shadow registers calculation but as you could see, once I get the indication for WRITE1 and READ1, the offset and index is available.

I know the code to detect STOP bit and convert stuff as above is not ideal but it is working or at least I believe it it working.

Again, many thanks for your suggestion and help.

void EZI2C_1_ISR_ExitCallback()

{

    uint8 idx;

    if (EZI2C_1_curStatus & EZI2C_1_STATUS_BUSY)

    {

        return;

    }

    if (EZI2C_1_IS_BIT_SET(EZI2C_1_CSR_REG, EZI2C_1_CSR_STOP_STATUS))

    {

        if (EZI2C_1_curStatus & EZI2C_1_STATUS_RD1BUSY)

        {

            EZI2C_1_curStatus = EZI2C_1_STATUS_READ1;

        }

        if (EZI2C_1_curStatus & EZI2C_1_STATUS_WR1BUSY)

        {

            EZI2C_1_curStatus = EZI2C_1_STATUS_WRITE1;

        }

        idx = 0;

        while (ezi2cShadowBuff[idx].regId != RPI_REG_END) 

        {

            // has any bytes of the register touched?

            if ( ezi2cShadowBuff[idx].regId >= EZI2C_1_rwOffsetS1)

            {

                if ((ezi2cShadowBuff[idx].regId + ezi2cShadowBuff[idx].numBytes) <= EZI2C_1_rwIndexS1)

                {

                    if (EZI2C_1_curStatus == EZI2C_1_STATUS_READ1)

                    {

                        ezi2cShadowBuff[idx].ezi2cStatus |=  EZI2C_1_STATUS_READ1;

                    }

                    if (EZI2C_1_curStatus == EZI2C_1_STATUS_WRITE1)

                    {

                        ezi2cShadowBuff[idx].ezi2cStatus |=  EZI2C_1_STATUS_WRITE1;

                    }

                }

            }

            idx++;

        }

        EZI2C_1_curStatus = 0;

    }

}

Regards

Shahram Amini