Hello @michaelym
I could not find documentation on how ECC is handled.
I understand that one error is corrected by itself.
What happens when there is more than one error?
For every 8 bytes of firmware memory ECC can correct one bit of data and detect 2 bits of error. One bit of error will be corrected. But the correction only occurs in cache, and the code in flash is still incorrect.
In case of 2 bit error the error is not corrected but can only be detected.
The CACHE_ECC_ERR and CACHE_ECC_CORR will contain information regarding Flash address where error was detected and corrected (in case of CACHE_ECC_CORR) and Flash address where error was detected (in case of CACHE_ECC_ERR). You can find more details about these registers in the PSOC 5LP Register TRM.
the datasheet says "an interrupt can be generated when an error is detected"Does the device just stop working?
Does it go to a default interrupt and stay in a while(1) loop?
Would it cause the WDT to be triggered and then the error will be detected again?
Yes an interrupt can be generated in case an error is detected. The Interrupt vector table (table 4-6) of the PSOC 5LP datasheet mentions about the cache/ecc interrupt.
The device should not stop working when the interrupt occurs, nor does the default interrupt stay in a while loop. But it is better to shutdown PSoC if an error is failed to be correct.
PSoC 5LP Register TRM provides more information regarding ECC Error detection and Interrupts (refer page 86).
In case you want to generate an interrupt in order to perform some task (like reading the ECC register) when the ECC error occurs you can do so by using the Global Signal component and setting the cache interrupt as the interrupt source:
Thanks and Regards
Ekta
Hello @michaelym
I could not find documentation on how ECC is handled.
I understand that one error is corrected by itself.
What happens when there is more than one error?
For every 8 bytes of firmware memory ECC can correct one bit of data and detect 2 bits of error. One bit of error will be corrected. But the correction only occurs in cache, and the code in flash is still incorrect.
In case of 2 bit error the error is not corrected but can only be detected.
The CACHE_ECC_ERR and CACHE_ECC_CORR will contain information regarding Flash address where error was detected and corrected (in case of CACHE_ECC_CORR) and Flash address where error was detected (in case of CACHE_ECC_ERR). You can find more details about these registers in the PSOC 5LP Register TRM.
the datasheet says "an interrupt can be generated when an error is detected"Does the device just stop working?
Does it go to a default interrupt and stay in a while(1) loop?
Would it cause the WDT to be triggered and then the error will be detected again?
Yes an interrupt can be generated in case an error is detected. The Interrupt vector table (table 4-6) of the PSOC 5LP datasheet mentions about the cache/ecc interrupt.
The device should not stop working when the interrupt occurs, nor does the default interrupt stay in a while loop. But it is better to shutdown PSoC if an error is failed to be correct.
PSoC 5LP Register TRM provides more information regarding ECC Error detection and Interrupts (refer page 86).
In case you want to generate an interrupt in order to perform some task (like reading the ECC register) when the ECC error occurs you can do so by using the Global Signal component and setting the cache interrupt as the interrupt source:
Thanks and Regards
Ekta
