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PSoC™ 5, 3 & 1 Forum Discussions

Gone
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Level 1
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Is there a way to do CSIO in Creator for a PSoC5 part?

Thanks

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ScottC.

Thanks for letting us know you were targeting RS485 type drivers.

Note:   Most RS485 drivers are slew-rate limited.  This means that their top data rate may be below 1Mbps.  Whatever drivers you use, check the maximum frequency it can support.

The RS-485 also has to arbitrate when to turn on the bi-polar drivers using an Output Enable (OE).  Switching the OE too fast might cause more than one node driver to be on the buss at the same time.

I've designed around two busses using RS-485 drivers.  In one case, the buss is limited to 9600 baud due mainly to the multi-node/long-wire configurations.

One of the BIGGEST issues of high speed serial networks is analog effects of transmission lines.

This can be a book of caveats in itself.   In fact, there are actually good books about this subject.

Here's some thoughts of common methods seen by successful high-speed networks:

Wiring configurations

The best non-amplified wired configuration to service multiple nodes on the same wire is a daisy-chain.  In a good daisy-chain configuration, it basically looks like a single long wire from the first node to the last node.   

AVOID star wiring method!!!  This is where many nodes are connected to a single node.   It looks like a 'star' from the wiring's perspective.  The major issue are signal reflections on any of the nodes.   

Remember that electrons travel near the speed of light.   When it originates from one node and reaches another it most likely will take some of the energy in the signal and reflect it back down the same wire and send it back down the line.   

These reflections can add or substract from the original signal causing a 'ringing' effect.   If the ringing effect is severe enough, it could either damage the driver or receivers or more likely cause receivers to see an opposite unintended logic transition.

The star pattern is more complicated as more star 'stubs' are on the line.  This makes the reflections more unpredictable.

There is an old wiring configuration rarely used called circular.  It is normally a node-to-node connection with a second node-to-node to pass buss requests on to the next node set.  It is normally not used any more.  It suffered from a LAN hanging when one of the nodes is powered down or not responding.

Line Terminations

Even in the "best case" daisy-chain wiring, you need to place impedance-balancing line terminators on BOTH ends of the buss.  If you're using a twisted-pair wiring scheme, 120 to 150 ohm resistors across the BUSS+ and BUSS- wires.

This is to minimize signal reflections as explained in Wiring Configurations .  In a daisy-chain the stubs are minimized but reflections can exist because there is a beginning and an end to the buss.  The terminators will absorb much of the energy as reaches each end before it can reflect.

The "Eye" Pattern

All high-speed data communications use what is called an "eye" pattern to judge the quality of the analog signal of the transmission line.  In general, it is a measurement of the ratio of the area between the transitions.  Ie.  eye_ratio = area_actual_eye/ area_perfect_eye.

A good eye is 60% or higher.  Less than this could yield bit errors.

Here is a link to more info about eye pattern issues:  https://www.edn.com/eye-diagram-basics-reading-and-applying-eye-diagrams/ 

Len_CONSULTRON_0-1674504013031.png

Adaptive Equalization

All Busses have parasitic analog elements that determine the quality of the driver's signal as seen by all the nodes.

Here are some of these qualities:

  • Line inductance
  • Line capacitance
  • Line termination (to minimize reflections)
  • Driver slew-rates
  • Driver current drive limits for source and sink
  • timing jitter
  • update: wire length.  This is the primary cause of time delays resulting in signal reflections.

There are specially designed drivers based on the physically layer of the OSI that provide automatic adaptive equalization to maximize the eye pattern.

Use a high-speed circuit designed to meet your requirements

There are commercial high-speed communication circuits available to meet your requirements.    Without excellent understanding of many of the analog effects I mentioned above (and more ...) your efforts can be fraught with problems.   If you're designing a system for production it is further complicated with "shortcuts" the customer may want to take to lower costs.   Then your field service rep will be kept VERY busy.

Good high-speed circuits support IEEE802 methods such as ethernet.   Although this might seem a bit costly, consider the costs of field service calls and dissatisfied customers.

There may be lower-cost HS circuits for buss drive.  However, it will most likely be an external circuit to the PSoC5.

Len
"Engineering is an Art. The Art of Compromise."

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Len_CONSULTRON
Level 9
Level 9
500 solutions authored 1000 replies posted 750 replies posted

Gone,

What is a CSIO?  If you're referring to "Clock-Synchronous Serial IO"  All the PSoCs support SPI and I2C.  The PSoC6 supports I2S.

Len
"Engineering is an Art. The Art of Compromise."
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Gone_0-1674165401036.png

 

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Gone,

The PSoC5 does not have a PDL MFS resource but it does have individual USART resources such as:

Len_CONSULTRON_0-1674224460734.png

Is this what you were inquiring about?

Len
"Engineering is an Art. The Art of Compromise."
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Len you mentioned the PSoC5 does have a USART resource.  I am a bit confused we are looking for a USART.  Basically we need RX, TX, and a clock so they can be in sync and so we can run as fast as possible.

thanks

ScottC

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Gone,

The PSoC5 does not have any fixed HW resources for data communication.

Depending on the configuration you want, it compiles UDBs (Universal Digital Blocks) into UART, SPI or I2C implementations.

Therefore, officially the PSoC5 doesn't come with a USART configuration.

Here are some suggestions that might help:

Suggestion #1

You can set up a SPI component to output both CLK and Tx and Rx data.   The issue here is if you need UART START, STOP and/or PARITY bits.  

For example, I just created a UART 8M1 Tx emulator using a 11-bit SPI component.  It works very well.  A bit more SW intensive.

If you don't need START, STOP or PARITY bits you can easily use SPI with CLK, MISO, MOSI and CS signals to very quickly support high frequency and reliable data transmissions, (> 8Mbps)   This is because the CLK signal transition is when to clock out or in the data.   

On a UART/USART, usually the transmit data rate is agreed upon and requires an input clock of at least 8x to decimate the actual data coming in.   This limits the top end of the data rate.  Add to it that START and STOP bits are there to resync the first bit of the byte to the timing state machine, it is further limiting the aggregate data rate.  

Additionally the actual UART/USART clock used may be different between the two communicating devices.  This leads to a frequency error that can be significant as the data rate increases.   Usually only about a 4% frequency difference can be tolerated before errors may show up (especially over longer cables due to propagation delay and capacitance effects and cable reflections.)

Suggestion #2

In theory you should be able to create a USART component using UDBs.   However, doing so is not for the "faint of heart".   This technique can be achieve by seasoned PSoC5 users.  The documentation is available from Infineon but they are many and somewhat scattered.

Suggestion #3

Can you share your specific design goals?   We on the forum might be able to suggest a better solution.

For example:

  • Are you required to work with an older established protocol that requires a USART?
  • What maximum data rate are you trying to achieve?
  • What is the maximum length of cabling or traces?
  • Is this a point-to-point connection or are there multiple "drops" to multiple n the same wire?

 

Len
"Engineering is an Art. The Art of Compromise."
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Len,

Thank you for your help.  To answer your questions you mentioned.  We would like to use an RS485 type of drive but add a third drive for a clock.  Currently we can have up to 10 or more device on our buss and our wire runs can be over 100 feet in length.  Currently we are running PSoC5 devices on all these nodes.  We are testing currently with just two nodes and we are seeing errors in our transmissions just as you mentioned if we run over 1Msbs.  We need to run at least 5Mbsps so we can get enough data transmitted for our system requirements. We really require the data and timing do be accurate to all nodes.

I did look into the UDB ... but as you mentioned I am not that seasoned to do this yet.  But it my get that if needed.

Thanks

ScottC

 

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ScottC.

Thanks for letting us know you were targeting RS485 type drivers.

Note:   Most RS485 drivers are slew-rate limited.  This means that their top data rate may be below 1Mbps.  Whatever drivers you use, check the maximum frequency it can support.

The RS-485 also has to arbitrate when to turn on the bi-polar drivers using an Output Enable (OE).  Switching the OE too fast might cause more than one node driver to be on the buss at the same time.

I've designed around two busses using RS-485 drivers.  In one case, the buss is limited to 9600 baud due mainly to the multi-node/long-wire configurations.

One of the BIGGEST issues of high speed serial networks is analog effects of transmission lines.

This can be a book of caveats in itself.   In fact, there are actually good books about this subject.

Here's some thoughts of common methods seen by successful high-speed networks:

Wiring configurations

The best non-amplified wired configuration to service multiple nodes on the same wire is a daisy-chain.  In a good daisy-chain configuration, it basically looks like a single long wire from the first node to the last node.   

AVOID star wiring method!!!  This is where many nodes are connected to a single node.   It looks like a 'star' from the wiring's perspective.  The major issue are signal reflections on any of the nodes.   

Remember that electrons travel near the speed of light.   When it originates from one node and reaches another it most likely will take some of the energy in the signal and reflect it back down the same wire and send it back down the line.   

These reflections can add or substract from the original signal causing a 'ringing' effect.   If the ringing effect is severe enough, it could either damage the driver or receivers or more likely cause receivers to see an opposite unintended logic transition.

The star pattern is more complicated as more star 'stubs' are on the line.  This makes the reflections more unpredictable.

There is an old wiring configuration rarely used called circular.  It is normally a node-to-node connection with a second node-to-node to pass buss requests on to the next node set.  It is normally not used any more.  It suffered from a LAN hanging when one of the nodes is powered down or not responding.

Line Terminations

Even in the "best case" daisy-chain wiring, you need to place impedance-balancing line terminators on BOTH ends of the buss.  If you're using a twisted-pair wiring scheme, 120 to 150 ohm resistors across the BUSS+ and BUSS- wires.

This is to minimize signal reflections as explained in Wiring Configurations .  In a daisy-chain the stubs are minimized but reflections can exist because there is a beginning and an end to the buss.  The terminators will absorb much of the energy as reaches each end before it can reflect.

The "Eye" Pattern

All high-speed data communications use what is called an "eye" pattern to judge the quality of the analog signal of the transmission line.  In general, it is a measurement of the ratio of the area between the transitions.  Ie.  eye_ratio = area_actual_eye/ area_perfect_eye.

A good eye is 60% or higher.  Less than this could yield bit errors.

Here is a link to more info about eye pattern issues:  https://www.edn.com/eye-diagram-basics-reading-and-applying-eye-diagrams/ 

Len_CONSULTRON_0-1674504013031.png

Adaptive Equalization

All Busses have parasitic analog elements that determine the quality of the driver's signal as seen by all the nodes.

Here are some of these qualities:

  • Line inductance
  • Line capacitance
  • Line termination (to minimize reflections)
  • Driver slew-rates
  • Driver current drive limits for source and sink
  • timing jitter
  • update: wire length.  This is the primary cause of time delays resulting in signal reflections.

There are specially designed drivers based on the physically layer of the OSI that provide automatic adaptive equalization to maximize the eye pattern.

Use a high-speed circuit designed to meet your requirements

There are commercial high-speed communication circuits available to meet your requirements.    Without excellent understanding of many of the analog effects I mentioned above (and more ...) your efforts can be fraught with problems.   If you're designing a system for production it is further complicated with "shortcuts" the customer may want to take to lower costs.   Then your field service rep will be kept VERY busy.

Good high-speed circuits support IEEE802 methods such as ethernet.   Although this might seem a bit costly, consider the costs of field service calls and dissatisfied customers.

There may be lower-cost HS circuits for buss drive.  However, it will most likely be an external circuit to the PSoC5.

Len
"Engineering is an Art. The Art of Compromise."
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Thanks Len ... looks like i am going to learn a lot on this project.  thank for your insight and direction.

ScottC

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I believe Len was referring to the synchronous nature of the interfaces he referred to.  But, they are not a USART as you are looking for.

BTW, which physical layer protocol are you looking to work with?
HDLC, Bi-Sync, other?

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