Svem_MZ,
Attached is a demo project showing DMA transfer from a 16-bit RAM buffer to the custom 16-bit Control Register. It utilizes custom component ControlReg16 (and a complimentaryStatusReg16) components which allow for simple DMA access. The ControlReg16 and StatusReg16 component are included into the project.
You can accommodate this project for DelSig_ADC to CReg16 transfer by changing DMA settings.
/odissey1
Figure 1. Project schematic. DMA transfers data from RAM buffer to CReg_1 on each Timer clock. When DMA transfer is complete, the program terminates.
Figure 2. UART Terminal output showing content of the Buffer, CReg_1 and SReg_1 registers.
Figure 3. Project annotation using PSoC Annotation Library v1.0
Sven,
There are two easy ways to solve this.
Here's one that more closely matches your suggestion:
The ADC EOC causes a DMA from the ADC data registers to the CR_ADC control register. The CR_thresh register is used by you to set the threshold to trigger an event such as an interrupt. The Dcmp can be set to the threshold type you want.
Another way is to use a Voltage Fault detector component available on the PSoC5.
This allows for 1 to 32 analog inputs and it uses two VDACs and two analog comparators along with some UDB logic to determine one of three stages of each pin: Undervoltage, Good, and OverVoltage.
Sven_MZ,
The DelSig-ADC is relatively slow, working in some kHz rate, so most appropriate technique would be using ADC interrupt and comparing the values in code. The other approaches could be justified only when working in MHz range, using SAR-ADC.
The SAR_ADC has digital output bus, which can be connected directly to the digital comparator. You can find a project using ADC_SAR_ex custom component (SAR_ADC modified with digital output bus) here:
ADC_SAR - Filter - VDAC streaming demo using DMA
Attached below is a demo project showing use of the ADC_SAR_ex output bus and digital comparator. The width of the output bus corresponds to ADC bit resolution.
Figure 1. Use of the ADC_SAR_ex digital output bus for digital comparator connection.
Svem_MZ,
Attached is a demo project showing DMA transfer from a 16-bit RAM buffer to the custom 16-bit Control Register. It utilizes custom component ControlReg16 (and a complimentaryStatusReg16) components which allow for simple DMA access. The ControlReg16 and StatusReg16 component are included into the project.
You can accommodate this project for DelSig_ADC to CReg16 transfer by changing DMA settings.
/odissey1
Figure 1. Project schematic. DMA transfers data from RAM buffer to CReg_1 on each Timer clock. When DMA transfer is complete, the program terminates.
Figure 2. UART Terminal output showing content of the Buffer, CReg_1 and SReg_1 registers.
Figure 3. Project annotation using PSoC Annotation Library v1.0
