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Hi,
Happy Holidays!
I just posted a new pre-component with Demo project to the "Code Examples" forum.
It is a 14-bit Voltage DAC using dithering technique to gain additional resolution beyond the inherent 8-bits of the Cypress VDAC8.
If I've piqued your interest, here is a link to the project thread and more information.
DVDAC14-14-bit-VDAC-using-the-Dithering-Technique
Enjoy!
"Engineering is an Art. The Art of Compromise."
Solved! Go to Solution.
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PSoC3 MCU
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PSOC5 LP MCU
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The DVDAC14 post has been updated with a PSoC3 version of the pre-component.
"Engineering is an Art. The Art of Compromise."
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Len,
Thank gou for posting a preview of the component.
Did you measure INL / DNL curves at 14 bits?
/odissey1
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/odissey1,
No I didn't measure the INL and DNL. I'm using the INL and DNL of the VDAC8.
I don't have equipment sensitive enough to measure every bit count. Maybe you're better situated.
In order to visualize some semblance of linearity, I use a PGA @ 50 gain to see the steps large enough on my scope.
Here's a scope pic of a 65 step ramp from 0.01V to 0.026V on the 4V range with the ramp going through the PGA@50.
The scope plot is on Display (Average of 1 sample) with a BW limit of 20 MHz.
Since the dithering is effectively a PWM of two consecutive VDAC8 counts, the DNL and INL should only be as good as the dithering bit pattern used at any of the dither DAC code values.
I tried to be careful to space the '1's and '0's as evenly as possible.
"Engineering is an Art. The Art of Compromise."
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Hi Len,
Thanks for sharing the solution with community 🙂
Best Regards,
Vasanth
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The DVDAC14 post has been updated with a PSoC3 version of the pre-component.
"Engineering is an Art. The Art of Compromise."