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PSoC™ 5, 3 & 1 Forum Discussions

Anonymous
Not applicable

Hi All,

   

Im looking at using a PSOC5 in a new project , and spent a wek or so reading up, and writing test apps. Got an idea now how most things (that I need ) can be done, but not DMAing or FIFO filling a data latch input of more than 8 bits ( using Dtype and status register) say up to 32 bit.

   

Has somebody created such a component? I would have thought it would be a useful addition to the components library

   

No doubt there will be lots more posts when I discover what I thought I understood is wrong!!

   

Many thanks 

   

Steve

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1 Solution
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

stevewidg,

   

Take a look on FIFO buffer example in PSoC Sensei blog (and many other educational examples there)

   

http://www.cypress.com/blog/psoc-sensei-blog?tid=All&date_filter[value]&page=1

View solution in original post

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8 Replies
Bob_Marlowe
Level 10
Level 10
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You will need to combine 4 UDBs to form a 32 bit wide component that you can access trough DMA. A job to program in verilog.

   

 

   

Bob

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Anonymous
Not applicable

Thanks Bob,

   

I was sorta afraid thats what you would say. I'm new to PSOC and that sounds like a pretty steep learning curve for newbie. A generic data latch sounds like a fairly standard component to want to me.

   

Once again thanks Bob.

   

Steve

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odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

stevewidg,

   

Take a look on FIFO buffer example in PSoC Sensei blog (and many other educational examples there)

   

http://www.cypress.com/blog/psoc-sensei-blog?tid=All&date_filter[value]&page=1

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Anonymous
Not applicable

Thanks Odissey1,

   

That looks like it will do the job, though looks like can only do 16 bit transfer due to DMA limit.

   

How come Cypress havent icorporated this in standard Library.

   

Regards

   

Steve

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Please check post by KeerthiRocks and updated FIFO project to capture 8 / 16 bit data parallely and buffer to a depth of level 4.

   

http://www.cypress.com/forum/psoc-5-architecture/fifo-sample-8-or-16-bitparallel-inputs

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Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

There might be other ways to implement what you want.

   
        
  • What is sitting on the outside of the PSoC and feeding it with data? A control signal will surely be provided to indicate valid data.
  •     
  • What are you now going to do with the 32 bit Item?
  •    
   

 

   

Bob

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Anonymous
Not applicable

Hi Bob,

   

Its data logging of totally independent inputs, no valid indicator available, which I want to control with either an internal clock up to as high a rate as can be achieved, or an external clock, then send a largish packet ( say 16KB+) of this down USB to be examined by a PC. For my current requirements I only need 16 bit transfer, I thought any solution would be up to 32 bit wide.

   

I don't know what the maximum burst data rate would be with PSOC5 , but the PSOC3 FIFO said it required 9 clocks per sample so under 10MHZ Is this correct?

   

Regards

   

Steve

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Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

maximum burst data rate What do you mean with that?

   

 FIFO said it required 9 clocks per sample Which FIFO, what are you sampling with??

   

You can have a clock for an input pin. look at pins datasheet page 23. Values from port can be transfered by a DMA channel.

   

 

   

Bob

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