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I am trying to capture a stream of bits into a buffer using a PSOC5LP board. I would like to capture roughly 40 bytes each burst at 8MHz.
This seems like a great job for a shift register and DMA.
Apparently shift registers output to a FIFO which needs to be triggered by accessing a status register before the output will update properly. Has anyone used a shift register and DMA like this before? How do you access the appropriate registers and is it possible to use a 32-bit wide shift register?
I will upload a sample project tomorrow (I have run out of work day now)
Thanks
Greg
Solved! Go to Solution.
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greg,
I see a bottleneck with DMA transfer speed, which is 11-14 clocks per byte, which would need the BUS_CLOK speed greater than 80MHz to handle 8MHz burst train. Possible solutions could be:
(i) using some hardware FIFO to intermediately hold the data,
(ii) directly reading by CPU w/o DMA,
(iii) use faster MCU,
(iv) overclock PSoC5 to 100+MHz.
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greg,
I see a bottleneck with DMA transfer speed, which is 11-14 clocks per byte, which would need the BUS_CLOK speed greater than 80MHz to handle 8MHz burst train. Possible solutions could be:
(i) using some hardware FIFO to intermediately hold the data,
(ii) directly reading by CPU w/o DMA,
(iii) use faster MCU,
(iv) overclock PSoC5 to 100+MHz.
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Thank you for the heads up, I hadnt realised transfer speed would be a bottleneck. I shall try using an SPI component instead.
Cheers
Greg
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Greg,
I might have misleaded you. If 8 MHz is a data clock speed, then it is only 1 MHz of byte speed, which DMA can handle easily.