Control a Sample Hold with a register

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xy_283156
Level 2
Level 2
        Hi, is it possible to use a control register to trigger a sample hold?   
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Anonymous
Not applicable
        Can you give us a bit more details?   
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Bob_Marlowe
Level 10
Level 10
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Using a control-register instead of a regular clock will work, there is at first no limitation for tle lowest frequency^. You should consider that the inernal capacity is very small in the area of fF (fempto Farad) and so will not be able to hold an output very long...

   

 

   

Bob

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ETRO_SSN583
Level 9
Level 9
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The PSOC device geometry input, which would be a reflection of Cgd, eg. the

   

hold capacitor, is 5 pF nominal. There is a droop spec in datasheet, with no value

   

given. You can easily test droop with  simple test bed and the delsigma, acquire

   

a sample at full scale, and measure time it takes to get to close to ground. The

   

droop largely a leakage value, and you can google for MOSFET leakage

   

contributors, IEEE papers especially, will give you an idea if it looks like a constant

   

curent source dominant contributor, which I think it is.

   

 

   

Then use Q = C x V, I = C x dV/dT to calculate the leakge. Note it is a strong f(T).

   

 

   

Regards, Dana.

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ETRO_SSN583
Level 9
Level 9
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Here is a clarification of the size of the S/H capacitor size from

   

the TRM -

   

 

   

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ETRO_SSN583
Level 9
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Interestingly found another schematic including T/H and shows a different

   

value for hold cap, I will clear up with Cypress ( here its 4 pF) -

   

 

   

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Anonymous
Not applicable

 As in the other thread, Cypress needs to update the datasheet.

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ETRO_SSN583
Level 9
Level 9
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I have posted a Case on this, as in the other thread.

   

 

   

Regards, Dana.

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