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yaga_3967241
Level 3
Level 3
50 sign-ins 25 sign-ins 10 replies posted

Hi,

We are using PSoC 5LP. In our workspace, there is one bootloader project and one bootloadable project, and they are linked together.

Before doing  PSoC FW update, we need to call Bootloadable_Load() from bootloadable project to put PSoC into bootloader mode.

We found that, after setting PSoC to bootloader mode by calling Bootloadable_Load(), instead of a software reset, PSoC does a hardware reset. For software reset, Bootloadable_Load() makes PSoC stay in bootloader mode forever until there is a SW update; For hardware reset, it follows bootloader component settings ( "Wait for command") in bootloader project, wait for the time we set and boots into bootloadable application.

My questions are: how to make Bootloadable_Load() just do software reset so IO PSoC stay in bootloader mode?

I found something as below that may cause a software reset change to hardware reset, but not quite understand:

Note When the voltage detection is enabled and the configured threshold is below VDDA/VDDD during
the software reset (SRES), the hardware reset (LVI reset) might occur. During the software reset, the LVI
reset might get enabled (default state of the RESET_CR3 register) and hence the hardware reset might
occur instead of the software reset.

 

Best regards,

Winston

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4 Replies
Vison_Zhang
Moderator
Moderator
Moderator
First comment on KBA 750 replies posted 250 sign-ins

With the LVI configured as an interrupt, if the low-voltage condition and a soft reset (such as software reset, watchdog reset, segment reset) occur simultaneously, there is a chance that the low-voltage condition persists when the device resets due to the soft reset source. This will result in the low-voltage condition causing a hard reset as well. If a hard reset occurs, it results in the clearing of the soft reset status register bits in RESET_SR0 and RESET_SR1. The implication is that any soft reset occurring in conjunction with the LVI interrupt event will not be properly reflected in
the RESET_SR0, RESET_SR1 status registers. 

Did you enabled LVI as interrupt in your firmware code?

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yaga_3967241
Level 3
Level 3
50 sign-ins 25 sign-ins 10 replies posted

I have no idea what it means by "LVI configured as an interrupt". How to config LVI as interrupt and how to verify it is configured that way?

Thanks,

Winston

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yaga_3967241
Level 3
Level 3
50 sign-ins 25 sign-ins 10 replies posted

Seems LVI is configured only via GlobalSignal. If that is the case, we are not using any GlobalSignal component so we are not configuring LVI as interrupt.

Thanks,

Winston

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Vison_Zhang
Moderator
Moderator
Moderator
First comment on KBA 750 replies posted 250 sign-ins

If LVI is not enable, chip shouldn't have a chance to be hardware-reset when  Bootloadable_Load() is called. 

1. Could you please monitor the VDDD and VCCD pin of chip when Bootloadable_Load() is called, exclude hardware reset caused by power glitch.

2. When Bootloadable_Load() is called how did you determine that the CPU was being in bootloader mode for "wait for command" time before jump to the application, instead of jumping straight back?  

3. Did you compiler Bootloader and Application use different compiler, I.E. one use GCC and another use MDK?  

4. Please share a project which can reproduce this issue(remove your own code, only leave necessary code to reproduce this issue), let me do some tests.

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