I am trying to read a status register at regular, short intervals. To do this I've connected a clock to my DMA drq signal and have set up the status register DMA through the DMA wizard. I am using all internal clocks just to test the DMA but I have not seen any successful memory transfer. Could you please look over my code and let me know of any errors? I have also attached an image of my Top Design.
/* Defines for DMA_1 */
#define DMA_1_BYTES_PER_BURST 1
#define DMA_1_REQUEST_PER_BURST 1
#define DMA_1_SRC_BASE (CYDEV_PERIPH_BASE)
#define DMA_1_DST_BASE (CYDEV_SRAM_DATA_MBASE)
DMA_1_Chan = DMA_1_DmaInitialize(DMA_1_BYTES_PER_BURST, DMA_1_REQUEST_PER_BURST,
DMA_1_TD = CyDmaTdAllocate();
CyDmaTdSetConfiguration(DMA_1_TD, 1, DMA_1_TD, TD_INC_DST_ADR);
CyDmaTdSetAddress(DMA_1_TD, LO16((uint32)Status_Reg_1_Status_PTR), LO16((uint32)CYDEV_SRAM_DATA_MBASE));
unsigned char* Receive_Data = (unsigned char*) CYDEV_SRAM_DATA_MBASE;
CyGlobalIntEnable; /* Enable global interrupts. */
for(i = 0; i < 200; i++)
You should use
CyDmaTdSetAddress(DMA_1_TD, LO16((uint32)Status_Reg_1_Status_PTR), LO16((uint32)&StatsByte)));
It is easier for us when you post your complete project, so that we all can have a look at all of your settings. To do so, use
Creator->File->Create Workspace Bundle (minimal)
and attach the resulting file, next time. 😉
One more question since you're already familiar with my project setup. I've found that my drq signal only captures properly up to ~7 MHz with a BUS_CLK of 75 MHz. A faster drq rate seems to cause the DMA to skip edges. Is there a max drq rate that the DMA can handle relative to the bus clock? I've looked at the PSoC 5LP Architecture TRM but it's not straightforward how quickly it can accept drq triggers. I would like to capture the status register data as fast as possible (at regular intervals).
See the updated higher speed project attached. Thanks.
Answering that question could be done best by Cypress directly.
At top of this page select "Design Support -> Create a Support Case" and describe your problem. Attach your latest project.
The TRM explains what the actual time needed for a transfer is. Basically its N+6 cycles for an interspoke transfer (e.g. peripheral to sRAM), and 2N+5 for an intraspoke transfer (e.g. sRAM to sRAM). This might be higher when the CPU blocks the sRAM (which always takes 2 cycles). And the the triggering takes another cycle (since it needs to be synced to the clock). That comes up to the 10 cycles for a transfer that you observe.