Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

PSoC™ 5, 3 & 1 Forum Discussions

muma_3294506
Level 1
Level 1
First like received

Dear Community,

I am fairly new to psoc5lp and have a "CY8CKIT-059 PSoC® 5LP Prototyping Kit" , trying to achieve the following task with it:

# sample both SAR ADCs simultaniously with sample rate of 768kHz (using external CLK of 24.576MHz)

# transfer ADC-conversion results via SPDIF transceiver component at sample rates of 48kHz or 96kHz (maybe 192kHz, if possible)

What I do know:

# SAR ADC has some limitations, depending on bit-depth, external/internal reference voltage. Lets settle for 10 bit and external reference (proper decoupling assumed).

# It is possible to transfer conversion results directly to SPDIF component via DMA, which saves a lot of MCU ressources

# It might also be possible to use a Digital Filter Block as well, i.e.: ADC -> DMA -> DFB -> DMA -> SPDIF . That would be benifitial for noise reduction/low pass filtering

# DFB can be programmed via assembler instructions

What I do not know and want to figure out with your help:

# depending on the output sample rate the ADC results have to be downsampled by a factor of 4, 8 or 16. In order to get the best possible SNR I would like to implement avereraging in combination with downsampling (otherwise I could set the ADC to exact same sample rate as the SPDIF ouput stream)

# I guess, it should be possible with a custom DSP-program, but I have absolutely zero assembler-skills

# I can imagine that a simple moving averaging algorithm could be implemented in software, using a end-of-conversion interrupt. BUT: (a) that would cause a lot of CPU load at 768kHz and (b) I am not sure how to attach this software data-handling process to the DMA

Since the MCU does not have anything else to do, a pure software solution (means: without DMA) is probably feasable, but I have concerns about the high CPU load.

Do you have any ideas concerning downsampling/averaging and DMA? How would you approach this?

regards!

1 Solution
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

muma,

Attached are two projects (full version and the stripped one) demonstrating DMA transfer from the ADC_SAR to the Filter component and then to the VDAC8 (for testing purposes). This should help you going. The project shows essential ADC, DMA and Filter settings and helps to understand the capabilities and limitations. The ADC sampling frequency is set to 48kHz, and Filter cut-off is set to 5kHz to demonstrate filtering technique. Project uses CY8CKIT-059 Prototyping Kit.

The full version of the project includes a signal generator, which frequency can be varied using simple rotary encoder. The DDS32 and WaveGen8 are already included in the project. You can download other community components from the Community space:

Re: DDS24: 24-bit DDS arbitrary frequency generator component

Quad Decoder with Button Switch component for rotary shaft encoders

PSoC Annotation Library v1.0

The stripped version of the project has no any custom components, but requires external signal (sine) generator as a source.

Neither version shows how to DMA from the Filter to the SPDIF component, but let's leave it for the later. To test and debug SPDIF version you will need a receiver (SPDIF to Analog).

/odissey1

Figure 1. Project schematic.

SAR-Filter_VDAC_01b_A.png

Figure 2. Output signal testing using VDAC.

SAR-Filter_VDAC_01b_B.png

Figure 3. Optional signal generator using DDS32 and WaveGen8 custom components (full version only)

SAR-Filter-VDAC_02a_C.png

Figure 4. Project annotation (full version) using PSoC Annotation Library v1.0

SAR-Filter-VDAC_02a_KIT.png

Figure 5. Project annotation (stripped version), which has signal generator stripped out.

SAR-Filter-VDAC_01c_stripped_KIT.png

Figure 6. Blue trace - 1 kHz, 4Vp-p signal input. Yellow trace - signal output. Magenta - sine reference. Notice that output signal amplitude is 4 times less that the original input signal, and is not centered around Vdda/2 as expected due to the ADC_SAR internal bug. Some solutions are possible to remedy this (later).

SAR-Filter_VDAC_01b_D1.png

View solution in original post

0 Likes
3 Replies
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

muma,

Attached are two projects (full version and the stripped one) demonstrating DMA transfer from the ADC_SAR to the Filter component and then to the VDAC8 (for testing purposes). This should help you going. The project shows essential ADC, DMA and Filter settings and helps to understand the capabilities and limitations. The ADC sampling frequency is set to 48kHz, and Filter cut-off is set to 5kHz to demonstrate filtering technique. Project uses CY8CKIT-059 Prototyping Kit.

The full version of the project includes a signal generator, which frequency can be varied using simple rotary encoder. The DDS32 and WaveGen8 are already included in the project. You can download other community components from the Community space:

Re: DDS24: 24-bit DDS arbitrary frequency generator component

Quad Decoder with Button Switch component for rotary shaft encoders

PSoC Annotation Library v1.0

The stripped version of the project has no any custom components, but requires external signal (sine) generator as a source.

Neither version shows how to DMA from the Filter to the SPDIF component, but let's leave it for the later. To test and debug SPDIF version you will need a receiver (SPDIF to Analog).

/odissey1

Figure 1. Project schematic.

SAR-Filter_VDAC_01b_A.png

Figure 2. Output signal testing using VDAC.

SAR-Filter_VDAC_01b_B.png

Figure 3. Optional signal generator using DDS32 and WaveGen8 custom components (full version only)

SAR-Filter-VDAC_02a_C.png

Figure 4. Project annotation (full version) using PSoC Annotation Library v1.0

SAR-Filter-VDAC_02a_KIT.png

Figure 5. Project annotation (stripped version), which has signal generator stripped out.

SAR-Filter-VDAC_01c_stripped_KIT.png

Figure 6. Blue trace - 1 kHz, 4Vp-p signal input. Yellow trace - signal output. Magenta - sine reference. Notice that output signal amplitude is 4 times less that the original input signal, and is not centered around Vdda/2 as expected due to the ADC_SAR internal bug. Some solutions are possible to remedy this (later).

SAR-Filter_VDAC_01b_D1.png

0 Likes
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

muma,

I added extended versions of the ADC_SAR-Filter-VDAC demo using DMA in Community Code section

ADC_SAR - Filter - VDAC8 streaming demo using DMA

It shows couple of ways to resolve ADC_SAR issues of low output signal amplitude. To achieve SPDIF output you would need to replace output source from VDAC8 to SPDIF component.

/odissey1

0 Likes

Hello! Had a busy week, sorry for the late response. Thank you very much. I'll have a look into it this weekend.

Actually my PCBs with analog frontend and SPDIF transceiver have arrived this week, so there will be some hands-on experience soon.

I'll keep you posted.

0 Likes