Level 1
Level 1

# Any idea to process 0.01Hz in PWM?

Good day,

I am newbie to PsoC. Recently, I am doing a project of improving impedance meter(original resources: Chris Keeser) which able to process with 0.01Hz frequency by using PSoC 5LP Developing Kit. The figures below shows the TopDesign analog circuit and digital circuit:

Analog Circuit

Digital Circuit

The frequencies were generated by using Divider(PWM) with the frequencies range 0.01Hz, 0.10Hz, 0.20Hz, 0.50Hz, 1.0Hz, 2.0Hz, 5.0Hz, 10.0Hz, 50.0Hz and 100.0Hz and the periods(in micro second) write into Divider are 250000, 25780, 12890, 5155, 2577, 1288, 515, 257, 51 and 25 respectively to the frequencies.

The problem discovered from the data sheet of Pulse Width Modulation was the range of period count can be wrote for the divider maximum for 16 bits wide resolution where the period assigned for 0.01Hz is 250000 which exceed the 16 bit wide range and the frequencies measured with oscilloscope showing the value x100Hz than the frequencies needed and waveform showing unstable at 100Hz.

Is there any suggestion for process the 0.01Hz to the circuit in another ways and solve the problems of generating correct frequencies?

Thank you.

Dawn

1 Solution
Level 9
Level 9

# Re: Any idea to process 0.01Hz in PWM?

Dawn,

Moto  and \odissey1 definitely have valid suggestions.

I'll provide another one for academic purposes.

As the clock to your PWM you are using the BUS_CLK directly.  This clock is the most efficient for allocating clock resources on the PSoC.

However if you change to using either "Auto" or "MASTER_CLK" instead, you can use a digital clock resource which has a 16 bit divider available for control of the input clock to your 16-bit PWM.  Together, you get a combined 32bits of division available to your application.

You already know how to change the PWM period.  To change the incoming clock divider just use:

Clock_SetDivider(uint16 clkDivider)  where clkDivider is the desired divider + 1.

Len

Len
"Engineering is an Art. The Art of Compromise."
6 Replies
Level 9
Level 9

# Re: Any idea to process impedance meter(Psoc 5LP) with 0.01Hz frequency

Hi,

I wonder if you can use Timer, which can have up to 32bit counter.

If you need 50% duty clock, adding a TFF may take care of it, with the divider/2.

Divider value 250000

Divider value 25

moto

Level 9
Level 9

# Re: Any idea to process 0.01Hz in PWM?

Hi,

I recalculate the math (elementary school level?).

If all you need is 0.01Hz to 100Hz, we may use 24bit Timer.

If I can provide 24KHz clock to the timer, like

If divider is 2400000, freq is 0.01Hz (period = 100s)

If divider is 240, freq = 100Hz (period = 10ms)

moto

Level 9
Level 9

# Re: Any idea to process 0.01Hz in PWM?

Dawn,

To get higher frequency range you can use DDS24 or DDS32 community components instead of PWM

DDS24: 24-bit DDS arbitrary frequency generator component

which provide 24-bit and 32-bit frequency range accordingly. As a bonus, unlike the PWM, with DDS you can directly set any frequency.

/odissey1

Level 9
Level 9

# Re: Any idea to process 0.01Hz in PWM?

Dawn,

Moto  and \odissey1 definitely have valid suggestions.

I'll provide another one for academic purposes.

As the clock to your PWM you are using the BUS_CLK directly.  This clock is the most efficient for allocating clock resources on the PSoC.

However if you change to using either "Auto" or "MASTER_CLK" instead, you can use a digital clock resource which has a 16 bit divider available for control of the input clock to your 16-bit PWM.  Together, you get a combined 32bits of division available to your application.

You already know how to change the PWM period.  To change the incoming clock divider just use:

Clock_SetDivider(uint16 clkDivider)  where clkDivider is the desired divider + 1.

Len

Len
"Engineering is an Art. The Art of Compromise."
Employee
Employee

# Re: Any idea to process 0.01Hz in PWM?

I'll provide yet another one.

If you want to get a high division ratio divider,  It is easy to cascade multiple dividers.

Because the propagation delay from the "en" input to "div" output cannot be ignored, the "div" output is synchronized with the "clk" input.

If you want a 50% duty clock output, please use a TFF at the last stage.

This prescaler implementation is a part of my frequency counter.  Please refer following repository for the project.

You can also see a BLOG article in Japanese.

Regards,

Noriaki

Level 1
Level 1