48 MHz to 24 MHz chip switch, how to fix fit.M0049 and mpr.M0014 build errors?

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adamelli
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I changed the device to the new chip, CY8C4125PVS-482:

community.infineon.com/t5/Knowledge-Base-Articles/Changing-the-Target-Device-PSoC-3-PSoC-5LP-in-PSoC...

I was previously using  CY8C4245PVI-482. Then, I built the project. Errors resulted.

The first error to fix is the clock speed 48→24 MHz (see imo.png). 
The remaining errors are:

  • fit.M0049: Pin guidance unavailable: Resource limit: Maximum number of Macrocells exceeded
  • mpr.M0014: Resource limit: Maximum number of Macrocells exceeded

What does "fit" and "mpr" mean? Is there reference documentation explaining these errors? I never heard of a macrocell before. Is there a generic solution to these errors?

 

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1 Solution

Hi.

Try this.
I don't normally show the UART pins.  You can delete the GPIO's on schematic, change UART Pins config tab to no show.  From cydwr window, pins tab, you'll see the outline of the 4125 and a list of pin signals (at the right) for assigning to pins.  You can dlick on a pin name, RX, and once it's high-lighted, drag it to the pin with a SCB RX name.  Do the same for the TX pin.

Doing the TX/RX pin assignments using this method, Creator takes care of sorting out the GPIO pad configuration.  That's the way I've always done it.

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