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JQ
Level 1
Level 1
Distributor - Future(GC)
10 replies posted 5 comments on blog First comment on blog

How to move the PSOC4 program to RAM and run it? Is there a routine in PSOC CREATOR, thanks.

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nin
Moderator
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50 solutions authored 100 replies posted First like given

Hi @JQ ,

 

Please refer to PSoC4100S How to set code in SRAM with GCC. A similar problem statement and solution have been addressed in this thread.


Best regards,

Nin

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Vison_Zhang
Moderator
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First comment on KBA 750 replies posted 250 sign-ins

你可以参考一下贴子 PSoC4100S Plus Flash Driver Running in sram  中分享的例程 

 
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nin
Moderator
Moderator
Moderator
50 solutions authored 100 replies posted First like given

Hi @JQ ,

 

Please refer to PSoC4100S How to set code in SRAM with GCC. A similar problem statement and solution have been addressed in this thread.


Best regards,

Nin

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odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

It seems that you want to speed-up you code by executing it from the SRAM instead of FLASH. I tried some codes found on he internet and couldn't see no improvement. It could be code-specific, but I found many comments, that that's what it is.  

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Totally agree..., there is no speed improvement when running code from SRAM in PSoC4 devices.  It boils down to the simplified internal bus structure that prevents any improvement.

That said, it is very useful to run code from SRAM when you want to upgrade the bootloader.

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That is good to know. Can any speed improvement be achieved by executing code from SRAM in PSoC5?

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Yes, 5LP can run faster when code execution is in SRAM provided it resides in the upper half of SRAM.  The lower half is shared with 'other stuff'.  However, the upper half of SRAM is only shared with DMA bus activity.  This is one of 5LP's architectural strengths..., multiple internal buss's.

The benefit for 5LP SRAM execution is it can ALWAYS happen in clock cycles with 0 wait states, whereas FLASH is prone to wait states (even using the FLASH accelerator you will encounter lots of wait states).

edit: Code can be executed from either the upper or lower half of 5LP SRAM.  Conflicting documentation (AN89610) suggested it could only be executed from the lower half.  This has since been clarified.  I had issues trying to get code to run in the upper half so reverted to the lower half.

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