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onetwo
Level 1
Level 1
25 sign-ins First reply posted 10 sign-ins

Hello

I am really struggling to implement a fixed duty (50%), variable frequency pwm output (controlled by a pot).  - I am trying to generate a variable (+modulated) clock frequency for an external chip.

The only way I seem to be able top do it is by adjusting both the period and compare (as period/2) simultaneously, which feels a little clunky.

would anyone have any other suggestions how this could easily be done?

 

Many Thanks

 

Nick

 

 

 

 

 

Any pointers how this might be done would be greatly appreciated. 

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1 Solution
Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

onetwo,

Another way to alter the frequency while keeping the duty cycle the same is to programmatically change the input clock frequency to the PWM.  This allows you to not touch the period or compare values.

However, depending on the frequency range you are trying to support, the frequency change steps may not be very linear.

Len
"Engineering is an Art. The Art of Compromise."

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4 Replies
Srivastav
Moderator
Moderator
Moderator
10 likes given 50 solutions authored 100 replies posted

Hi Nick

You pointed out correctly, In order to maintain 50% Duty Cycle we must maintain a ratio of 1:2 for Compare/Period. 
When you say you want to have Variable frequency of the PWM signal with 50% duty cycle. Can you please explain how often you want to change the frequency? Which Development Environment are you using? 

 

Thanks & Regards

Arpit Srivastav

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LuNo_297436
Level 3
Level 3
First solution authored 10 replies posted 10 questions asked

Hi Nick,

It also depends on what frequencies and resolution  you want to achieve .

I have made this on a PSOC1 and only for audio frequencies.

You will need 2 TCPWM (counters)or something similar connected in cascade in the following way:

Connect the clock input  of a 16 bit counter  to 24 or48 Mhz , the output of this counter will be the overflow bit (terminal count on PSOC1) this is a pulse which will feed the clock input of the second counter.

Set the  second counter to the fixed ratio you need , in this case 1:2 (50%) and modulate the period of the first counter.

I hope i have explained it well.

Best regards

Luis

Len_CONSULTRON
Level 9
Level 9
Beta tester 500 solutions authored 1000 replies posted

onetwo,

Another way to alter the frequency while keeping the duty cycle the same is to programmatically change the input clock frequency to the PWM.  This allows you to not touch the period or compare values.

However, depending on the frequency range you are trying to support, the frequency change steps may not be very linear.

Len
"Engineering is an Art. The Art of Compromise."
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DennisS_46
Employee
Employee
100 sign-ins 50 likes received 50 solutions authored

Len is correct. You change the input clock to the PWM by changing the clock divider that drives the PWM. The wider the frequency range, the greater the deviation from straight line. For example, if the frequency range is 1.5:1 (e.g. 4000 to 6000 Hz), the mid-range error is about 4%. The good news is that while it is to some degree non-linear, it is always monotonic.
---- Dennis Seguine, PSoC Applications Engineer

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