PSoC™ 4 Forum Discussions

Hello

Define current time and date
Define first alarm time and date
Define second alarm time and date
Define alarm flag1
Define alarm flag2

        If alarmFlag1 is set   alarmFlag1 = 1u;

      and  If first alarm time ,date match with current time,date  

            Then perform following task    

              Alarm_LED_Write(1);

       CyDelay (100);

       alarmFlag1  = 0u;

      Alarm_LED_Write(0);

    alarmFlag2 = 1u;

      If second  alarm time ,date match with current time,date  

            Then perform following task    

   Alarm_LED_Write(1);

       CyDelay (5000);

       alarmFlag2  = 0u;

      Alarm_LED_Write(0);

how to execute two alarm in different flags ?

Hi. I have a few cy8c4124pvi-432. If the Vdd (=Vccd) voltage exceeds 4.5 V they burn! What am I doing wrong? Please help!

Hello Cypress World:

Evidently, the Cypress API macro below, that resides in the Cypress API file BLE_gatt.h, is erroneous:

/* Macro to get start handle of attribute

   Start handle is only meaningful for characteristic and

   service declaration */

#define CYBLE_GATT_DB_GET_START_HANDLE(handle)\

        cyBle_gattDB[(handle)-1u].connHandle

The cyBle_gattDB variable is a CYBLE_GATTS_DB_T data type as for example:  const CYBLE_GATTS_DB_T cyBle_gattDB[0x34u] in BLE_gatt.c.

The CYBLE_GATTS_DB_T does not have a connHandle element but does have an attHandle element as shown below:

/* GATT database structure used in the GAP Server */

typedef struct

{

      /* Start Handle: Act as an index for querying BLE GATT database */

    uint16                    attHandle;

    /* UUID: 16 bit UUID type for an attribute entry, for 32 bit and

       128 bit UUIDs the last 16 bits should be stored in this entry

       GATT DB access layer shall retrieve complete 128 bit UUID from

       CYBLE_GATTS_ATT_GENERIC_VAL_T structure. */

    uint16                    attType;

    /* The permission bits are clubbed in to a 32-bit field. These

        32-bits can be grouped in to 4 bytes. The lowest significant byte

        is byte 0 (B0) and the most significant byte is byte 3 (B3). The

        bytes where the permissions have been grouped is as given below.

           * Attribute permissions (B0)

         * Characteristic permissions (B1)

         * Implementation specific permission (B3, B2)

       */

    uint32                    permission;

    /* Attribute end handle, indicating logical boundary of given attribute. */

    uint16                    attEndHandle;

    /* Attribute value format, it can be one of following:

        * uint16 16bit - UUID for 16bit service & characteristic declaration

        * CYBLE_GATTS_ATT_GENERIC_VAL_T attFormatValue - Buffer containing 32 bit

            or 128 bit UUID values for service & charactertistic declaration

        * CYBLE_GATTS_ATT_GENERIC_VAL_T attFormatValue - Buffer contraining generic

            char definition value, or generic descriptor values

     */

      CYBLE_GATTS_ATT_VALUE_T       attValue;

 } CYBLE_GATTS_DB_T;

Is it true that the line of code below in the Cypress API file BLE_gatt.h needs to be changed

FROM:

        cyBle_gattDB[(handle)-1u].connHandle

TO:

        cyBle_gattDB[(handle)-1u].attHandle

Thank you,

Tim

Hi,

I'm having an issue where the set clock on one of my 4245AXI in 44TQFP does not match the actual clock. When the system clock is set to 48MHz and a pin set to generate a 1MHz clock, the micro only generates a 290KHz clock. When the system clock is set to 14MHz, a 973KHz clock is generated and when system clock is set to 5MHz a 2.69MHz signal is generated. So it seems the internal main oscillator is stuck at 13.5MHz. 

When I run the same code on another 4245AXI on cy8ckit dev board, it generates 1MHz no issue. So I believe the microcontroller hardware is faulty. 

The problematic microcontoller is on a PCB I designed, I was wondering if this was a common issue? 

Thanks

Hi all.

I managed to create my first PSoC custom component. It is written in verilog, and it contains a status and a control register, along with a datapath. Now, I'm trying to figure out how to write my API files so I can access these 2 registers from the CPU code. I know how to have the IDE create the files (that part is well-documented), but don't know what to put inside my .c and .h files to get to the underlying hardware.

In my project's cyfitter.h file, I see a bunch of long and scary #define names for the registers that appear in my instatiated, custom, verilog component. I don't really know where to begin to wrap these in an API. Since I am using the standard status and control registers inside my verilog code, I was *hopeful* that APIs would be auto-generated for those, and then I would just need to manually create a wrapper API at my componet level to call the easy read/write API of the status and control register components. No such luck.

Is there any help anyone can offer on how to make an API for a verilog custom coponent that needs to access its embedded status and control register components? This would seem like a pretty common use-case to me, but I'm VERY new to PSoC. 

I've purchased Cy5674 module, which gives option to connect antenna. On every picture was antenna together with module.

But when module arrived, they say: "sorry Antenna was too expensive for You".

Now I run two exactly same examples. One works (without antenna) other not.

What now?

I guess Cypress say wrong antenna. It will be a long, long story

Hello, I am playing around with the CY8CKIT-042-BLE, which includes the CY5670 CySmart USB dongle.  I like CySmart's ease of use, but for heavy duty debugging, would like to see the wire packets.  Is there a Wireshark support like on the Nordic's PCA10000 USB Dongle?  Please forgive me if my Bing search should have been more exhaustive.