PSoC™ 4 Forum Discussions

There doesnt appear to be a description on the PSoC4 Cap sense datasheet (2.40) about CapSense_NormalizeWidgets(). What does it normalize?

Hello everyone,

I'm trying to examine the DC current(range form -5A to 5A) on a user-circuit Vss wire using SARADC and Opamp components of "CY8C4247 /PSoC 4", the attachment is the demo circuit.
R0 equals 0.01ohm.

Since the difference voltage between Vi+&Vi- is small(50mv under 5A condition), with Opamps to amplify the voltage difference of ADC differential input ADC_in+&ADC_in- by 19.18times(gain=19.18). I wonder if this application would work properly?

signals Vin+&Vin- equals SARADC channel1 input+&input- in schematic demo2.

thx a lot

Hi,

    In my application we are attempting to perform quantitative capacitance measurements using the CY8C4247. I realize that this is not an application the chip was designed for and we likely will have to do our own qualification. There are a couple of major problems we are having. The following the the model we use to convert the raw counts into capacitance. It is derived from your capsense design guide. (mdac,cdac,sdiv) are parameters used for the capsense component. We are using PRS-12 to improve linearity. 

def toPf(count, mdac,cdac,sdiv, t=0,cc=0,cm=0,cadc=0):
   uaperbit = 1.2 * 1e-6; #1.2ua per bit

   cdac = mdac * (uaperbit + t*cm); 
   mdac = cdac * (uaperbit + t*cc); 

   cmax = ((1<<16)-1)
   vref = 1.2 + t * cv
   fsw = 48000000.0 / (2 * sdiv) / 2; # by 2 for PRS!!!!

   count += cadc*t

   count = max(0,min(cmax,count))
   cs = (count * mdac) / (cmax * vref * fsw) + cdac / (vref * fsw)

   return cs * 1e9

The first question is, why does changing cdac/mdac result in a change in the measured capacitance value? This does not really make sense from the model. 

Secondly, we are attempting to fit this model to observed data over a temperature range in order to derive the thermal coefficients. However it does not fit well. I suspect that our model is not good enough. Is there another theoretical model of capsense operation? This one does not include any term for the external Cmod capacitance which should have some effect on the measured value. Also we are using shield and I'm guessing that varying shield drive may cause issues. 

Lastly, now that SP2 is out, CSX is an option for us. Is there any information available on CSX temperature effects? I could not even find a way to convert CSX measurements into capacitance values. 

Any advice would be much appreciated. 

Thanks,

Jon Pry

I'd like to wake my PSOC4BLE system from deep sleep using a push button switch. The button, when pressed, grounds a pulled-up GPIO pin. I want to generate an interrupt when the button is pressed, and wake the system.

I normally debounce the switch in code, or with the Debounce 1.0 component from the library.  I am following the debouncer example in the PSOC examples library, where the isr connects to the debouncer output. 

The Debouncer requires a clock input, but I only have access to the HFCLK as my reference clock. This is shut down in deep sleep, so the debouncer does not run, and therefore the interrupt is not triggered when the button is pressed. Is there a way to select the LFCLK? I only have access to the Auto and HFCLK in the drop-down when configuring the Debouncer component.

If there isn't a way, what is a good way of debouncing when waking from deep sleep?

Thanks in advance.

The built in comparators within the PSoC4 chips can be configured with hysteresis, but this is internally set to 10mV.

I'm trying to do a simple level crossing detection using an analog input, a comparator and the IDAC with external resistor, but due to the noise associated with the input signals (I suspect there is a bit of noise on the voltage generated by the IDAC, as well as on my incoming AC signal), I'm getting a series of pulses around the transition point, rather than a clean positive going signal.

Ideally, I'd like to increase the amount of hysteresis so that I can avoid this problem.  The only idea I have really been able to come up with is to adjust the IDAC value as the first step in my ISR using IDAC_8bit_SetValue() so that once I've serviced the ISR, and released control back to the main loop, there is a larger voltage difference between the two signals on the comparator inputs.  At some suitable point afterwards, I then have to set it back to its normal value (I'm measuring a 100Hz signal, so I should have plenty of time to reset the IDAC value back prior to the next occurrence of my level crossing).

I've tried this, and it certainly improves things, but I'm still not getting a nice clean signal on the output of my comparator.

Has anyone ever been able to improve on the default 10mV of hystersis without resorting to having a hardware comparator or putting some brute force filtering on the input signal?

Mike

I have created a custom service with a notify characteristic that sends an uint8 array with a size of 20.

How do I increase the size to 60? When I increase to anything over 20 it stops working.

I tied increasing the MTU without success.

Regards, Paul.

Hi All,

I am using an ADC_SAR_SEQ component on the CYBLE022001 module. I would like to measure two channels having a different Vref value; VDDA for the first channel and internal 1.024 for the second one.  Does anyone know how to change the reference value within the code? I looked for this information in the datasheet and I didn't find it.

Thanks in advance,

Jurgi