PSoC™ 4 Forum Discussions

Hello，

当我使用CY8C4146LQS-S423芯片的AD采集功能时，遇到一些问题。当电压值在7V以下时，采集到AD值偏差会很大。

我使用的PSoC creator配置是：

芯片外围电路是：

AD值获取函数使用如下：

Type_sHWord wshPwrCtrlADCnvVDATA(void)
{
Type_uHWord auhADTimeOutCnt;

auhADTimeOutCnt = CLEAR;

ADC_SAR_Seq_1_StartConvert();

while ((CLEAR == ADC_SAR_Seq_1_IsEndConversion(1)) && (auhADTimeOutCnt < 0x140))
{
auhADTimeOutCnt++; /* A/D Convert TimeOut Counter */
}

wshPwrCtrlVDataADValue = ADC_SAR_Seq_1_GetResult16(PWRCTRL_BATT_ADC_CH0); /* Get A/D Value */

ADC_SAR_Seq_1_StopConvert();

return (wshPwrCtrlVDataADValue);
}

我怀疑可能是配置错了，能帮忙解决这个问题吗？

Hi~

I heard that there is PSoC 4100S Max series in PSoC line.

I hope to receive datasheet for it. Becuase I cannot find it in Infineon Web site.

Thanks alot

BRs

In PSoC4000S Device-Family there are devices with 48MHz and 24MHz max. CPU speed. The term 'CPU speed' is used in PSoC4000S data sheet and it's not exactly clear to me what this means.

For PSoC4000S devices with max. CPU speed of 24MHz,  which clock is limited to 24MHz?

1. Clock frequency of IMO is max. 24MHz
2. Clock frequency of HFCLK is max. 24 MHz
3. Clock frequency of SYSCLK is max. 24 MHz

If the term 'CPU speed' corresponds to SYSCLK frequency, is it possible to use higher clock frequencies for IMO and HFCLK? For example IMO = 48MHz , HFCLK = 48MHz, SYSCLK = 24MHz

Does the max. CPU speed only restrict CPU core clock or peripheral clocks as well?

Dear Sirs and Madams,

We are having trouble setting the I2S address to DST of DMA.

We know can configure DMA for I2S with HAL, but can't configure it with PDL only.

It seems that I2S cannot be set as "Destination" for DMA.

The I2S of this PSoC4S MAX cannot be connected with the DMAC without using HAL. right?

Regards,

I have been trying to export a Psoc4 Creator project into Keil uVision, 

the export to v5 just didnt work at all, it seems uvision does not longer support the generated files.

exported the project for v4 uVision and then converted to a v5 project

at first I wasnt able to compile it 

because there was two empty files referenced on the linker cycodeshareexport.ld / cycodeshareimport.ld ? any idea what this files should have, uvision was unable to find them I guess because they were empty.

I made sure the compiler used was the same as in PSOC creator ARM GCC 5.4 (from psoc creator folder)

the program compiled but somehow the hex file is not in the right format, I have tried adding the compiler flags but no luck, so the kitprog and miniprog are not allowing the programming to happen (the project runs and debugs fine from creator)

it would be great if someone can share a working configuration for the keil project!

linking...
creating hex file...
".\test.hex" - 0 Error(s), 264 Warning(s).
Build Time Elapsed: 00:00:06
Load "C:\\Users\\Admin\\Documents\\test.cydsn\\test.hex"
Failed to set hex file: Hex File parsing failure. Unknown record type.
Programming Failed!
Error: Flash Download failed - "Cortex-M0+"
Flash Load finished at 16:50:04

Not sure where to go from here.. there is not much details on the logs either

Hi, 

As I am not able to post on the previous posting,  please refer to the following link for the project source code

https://community.infineon.com/t5/PSoC-4/PSoC4-Power-Mode/m-p/362805#M43041

Since I have only 1 PSoC4 CY8CKIT-149 board and unable to order more, I would like to know when executing the sleep and deep sleep mode using the attached project, what is the current value measured across J3 at your side. 

Please help to provide your measured result.

Thanks.

I am using a ADC_SAR_Seq component and  using the internal range detection two of the channels. However I want to distinguish in an interrupt which channel  is being tripped by my range setting.  Is this possible to do, and if so how would I do it?

Thanks

Dear Sirs and Madams,

Please tell us about the fluctuation of the VDD voltage supplied to PSoC4S.

Currently, 3.3V is supplied to PSoC4S.

At this time, the power supply voltage fluctuates within the range of 2.9V to 3.3V due to external factors.

This fluctuating voltage range is within the operating range specified in the datasheet.

Naturally, I think that countermeasures using "snubber circuits" or "LC filters" are necessary, however Can the PSoC4S expect normal operation in this state?

Since PSoC4S has an internal regulator, do you think there is no problem with fast fluctuations such as spike noise or slow cycle fluctuations as long as they are within the operating voltage range?

Regards”

Hello all,

Is it possible to configure the LIN slave node as a passive listener only?
It is because of the situation below: We are going to install a separate system in the car. Actually we don't need LIN, but we need a signal from the master node, which triggers our system (or we will tap the signal somehow else). I also have the LDF file and wonder what happens if I pretend to be a slave node and basically do nothing but wait for the signal. Would this be possible or would I block the already existing node?

Best regards

Michael