Can I use bluetooth SDK version 5.0 with CYBLE-022001-00?
Because I found PSoC 4 BLE use 4.2 BT Block as BT SDK.
But actually Customer introduce this module as BT 5.0 Compliant to the end customer.
I've already known this module registed as bluetooth 5.1
But our customer concerned about Bluetooth SDK version.
If it cannot be updated as BT 5.0, then they should think about other models.
Could you please check the attached picture ?!
In the picture, we can see "GUARD" and "SHIELD" pins.
I feel confused about these 2 pins.
Does PSoC 4 have these 2 pins ("GUARD" and "SHIELD") !?
I think these 2 pins are all ground (GND). Am I right ?!
Thank you so much.Show Less
/* Once watchdog counter reaches match value interrupt is generated */
/* Configure WDT to be 14-bit wraparound up-counter - 2 MSb is ignored */
/* Start the WDT
* Enables watchdog timer reset generation. CySysWdtClearInterrupt()
* feeds the watchdog. Two unserviced interrupts lead to a system reset
* (i.e. at the third match).*/
CySysWdtClearInterrupt();//Feeds the watchdog
Please refer to the attached file,,,
for the button 0, the setting is 1 "sensing element"
for the button 1, the setting is 2 "sensing elements"
I would like to know in what condition a button needs 2 or more sensing elements.
Thank you so much.Show Less
I have a legacy workspace which uses PSoC 4 BLE (CYBLE-224110-00). There are 3 projects in there: a launcher, a stack and an application project. The application project has a Bluetooth Low Energy component (3.54) which is in "profile only" mode; the stack project also has a BLE component which is "stack only". Basically exactly what's explained in the upgradeable stack example.
There are devices out there with this firmware.
Now I'd like to rewrite the application project. The stack and launcher should not be touched in any way.
My goal therefore was to setup a new workspace, create one (single) project in there, with a BLE component (in the correct version) in "profile only" mode (and a bootloadable component of course). I want this project to use the stack from the old workspace; without having to "see" anything from the stack/launcher projects or having to compile them and so on.
Therefore I took the following files from the Stack project:
and copied them into the new workspace; and linked to these files from the BLE component dialog (for CyBle.cysa) and the Bootloadable component dialog (elf and hex file).
When I try to build the project I get:
.... arm-none-eabi-gcc.exe -mcpu=cortex-m0 -mthumb -I. -IGenerated_Source\PSoC4 -Wa,-alh=.\CortexM0\ARM_GCC_541\Debug/CyLFClk.lst -g -D DEBUG -D CY_CORE_ID=0 -Wall -ffunction-sections -ffat-lto-objects -Og -c Generated_Source\PSoC4\CyLFClk.c -o .\CortexM0\ARM_GCC_541\Debug\CyLFClk.o arm-none-eabi-gcc.exe -mcpu=cortex-m0 -mthumb -I. -IGenerated_Source\PSoC4 -Wa,-alh=.\CortexM0\ARM_GCC_541\Debug/cy_em_eeprom.lst -g -D DEBUG -D CY_CORE_ID=0 -Wall -ffunction-sections -ffat-lto-objects -Og -c Generated_Source\PSoC4\cy_em_eeprom.c -o .\CortexM0\ARM_GCC_541\Debug\cy_em_eeprom.o arm-none-eabi-as.exe -mcpu=cortex-m0 -mthumb -I. -IGenerated_Source\PSoC4 -alh=.\CortexM0\ARM_GCC_541\Debug/CyBootAsmGnu.lst -g -W -o .\CortexM0\ARM_GCC_541\Debug\CyBootAsmGnu.o Generated_Source\PSoC4\CyBootAsmGnu.s Error: prj.M0265: Could not find bootloader output file cycodeshareimport.ld, which is required for code sharing. --------------- Rebuild Failed: 03/03/2022 12:15:08 ---------------
So it is missing some cycodeshareimport.ld file. I do have this file in the old application project (in Generated_Source/PSoC 4). Copying that file to the new project doesn't change a thing.
Where / How is this file referenced?
As you can see; this is not even a linking error, but an error by the PSoC Creator thrown before even attempting to link the project.Show Less
Trying to use the RTC component, seconds advance appx 1/5th speed.
I routed the clock to a pin to scope it, the signal bounces between 4 and 7 kHz, and definitely isn't square. I expected some distortion from lengthening the wires, but this is excessive.
I even loaded a blank project, with just the clock and pin, no change.
From what I can find, the in internal crystal is either enabled or not, I cant find any adjustments.Show Less
i'm using an old cypress evaluation board cy8ckit-049-42xx. I can program it with the miniprog3 but I would like to program it with the kitprog2 that is attached to the kit board.
Psoc creator will not recognize the board when I plug the kitprog2 into the usb port and neither does psoc programmer.
I can plug the kitprog2 into the usb port and it makes a noise and shows up on device manager as usb serial port. the driver is cypress usbconsolewindowsdriver64.sys. I tried updating the driver but is says I have the latest one already installed.
What do I do to get the kitprog2 to be recognized by the programmer? Right now I'm just trying to program the board with the blinking led example.Show Less
i'm using a PSoC4 [4100S Plus] and i'm trying to add to my project an "Emulated EEPROM" component.
As described in the "Em_EEPROM" component datasheet i've compiled the project to generate a linker script file [cm0plusgcc.ld], i've renamed it [custom_cm0plusgcc.ld] and i've modified it in the following way to allocate 1024 bytes of "emulated EEPROM" at the top of the flash [CY_METADATA_SIZE and CY_MY_EEPROM_SIZE are defined at the top of the linker script and their values are respectively 64 bytes and 1024 bytes].
.my_emulated_eeprom (LENGTH (rom) - CY_METADATA_SIZE - CY_MY_EEPROM_SIZE) : ALIGN(8)
Now if i add in my project an array of 1024 bytes allocated in the "my_emulated_eeprom" section the build failes and gives me the following error : "region "rom" overflowed by 88 bytes".
Of course if i modify the linker script in the following way everithing works correctly.
.my_emulated_eeprom (LENGTH (rom) - CY_METADATA_SIZE - CY_MY_EEPROM_SIZE - 88) : ALIGN(8)
So this is my question : what's allocated at the top of the flash?
Looking at the linker script i thought that at the top of the flash there was just the metadata section [with the size pre-defined at the top of the linker script (=64 bytes)]
Thank you so much in advanceShow Less
i am new to PSoC and i try to talk via SPI to a communication peripheral hardware. But there are a few type definitions ... missing. I would like to use PDL verion 2.1.0 to implement my interrupts and other things. I tried to include cy_pdl.h to my project, but i got build error: cy_pdl.h not found. In fact cy_pdl.h is in PDL version 3, not in 2. But how to deal with it? How can i speak SPI with PDL in PSoC4.
I found lots of documents, doing it like PSoC6. But PSoC4 needs version 2 ... so i am a little bit confused.
Is there a possibility to use PDL SCP_SPI with PSoC4 or not?
I'd like to use the user SFlash of PSoC 4100S series chips, but I'm not sure if the Trim setting is here too.
Because I see below from "PSoC 4100S - 4100S Plus Architecture TRM.pdf".
Is the SFlash here different from the user SFlash? The starting address of SFlash is 0x0FFFF000, and the starting address of user SFlash is 0x0FFFF200?Show Less