PSoC™ 4 Forum Discussions
Hi sir,
I have a basic question, the specific difference between CY8C4247LQI-BL463 and CY8C4247LQI-BL483? What does asset code A and asset code B mean?
Thanks.
Show LessHello.
The following error message is displayed after I open CE195286 sample project.
Why does this error message occur?
If TopDesign_01.cymacro is deleted, this error message will disappear.
Best Regards.
Yutaka Matsubara
Show LessHi, this discussion is a follow-up on my older thread Developping CapSense trackpads with PSOC4 and 6 . I basically need a Cypress expert to validate my work before I buy the chips and fab the boards!
I have a first design of a CSX touchpad PCB with an embedded PSOC 4100S chip (CY8C4125AZI-S433).
I have mainly been referring to https://www.cypress.com/file/46081/download this design guide during my PCB design, and mainly tables 7-6 to 7-8 and figures 7-24 and 7-25 (p. 123) displayed here:
top layer (fig 7-24) bottom layer (fig 7-25)
I will now briefly describe what I managed to design so far before asking my questions!
Project Description
I integrated a 7x7 CSX touchpad into my design. There are multiple resources for implementing buttons or sliders, but I find it harder to develop touchpads (I often have been referred to the 40xx pioneer kit touchpad design), this is why I wanted to share my design before prototyping to make sure there are no big design flaws. Here, we see my design. Top layer has the CSX widget, surrounded by a 25% hatched GND plane. There is another ground plane (completely filled) on the higher half of the PCB. The bottom layer has the PSoC, the traces to the capsense, and a ground plane surrounding the top layer's hatched GND plane. Basically, I tried copying the groundplanes illustrated on fig 7-24 and 7-25.
*Note that I did not implement a shield in my app, so I did not add a 17% hatched pattern to my bottom layer under my capsense widgets. The bott layer (right) is empty, there is just a ground layer surrounding the borders with vias to help reduce gnd inductance.
Top Layer Bottom Layer
Questions
1. Star connected ground. I want to make sure my ground makes sense. Here I show my ground connections viewed from my bottom layer. Does it make sense?
Next is still linked to my ground, but refers to how I designed my top layer.
2. the full ground plane on the higher half of the board is right next to my hatched ground plane, but there is a gap between them. They are not directly connected, as I believed would respect the central star ground configuration. they are connected together with vias and traces on the bottom layer as shown on the right side. I am not too sure it is what is best. Should I completely short the 2 top layer planes together and remove the gap?
Still on top layer...
3. The full ground plane on the higher half of the board goes above the capsense RX and TX traces, which I believed was a problem but fig 7-24 does exactly that. I am confused because I though this would couple GND to my traces, thus reducing Cm.
5. Right now, I have kept the solder mask above my sensing elements, but in my last design, I removed it completely, so my sensing elements were bare copper. Which one is best? If I keep the solder mask, can I write silkscreen directly on top of my elements? I wanted to write like RX1, TX2, etc. on the corresponding elements
6. As one last small question, I was wondering if adding mounting holes and screws on the corner of my board could be a problem with capsense? I think I have read this somewhere in the documentation but I can't find it anymore.
There are quite a few questions in my thread, I am sorry, but I tried to be as clear as possible so the most people could benefit from your answers! Thanks again.
Show LessHello.
Customer is considering measuring input pulse width using attached PDF method.
Device is PSoC4.
“reload” is executed at the timing of input signal rising edge.
And “capture” is executed at the next rising edge.
So they are considering measuring motor rotation speed by counting number of pulses of “A” period of attached file.
Is it possible to do what they want with attached PDF method?
Input signal is connected to both “reload” and “capture”.
How does PSoC4 work in this case?
Does it work in an order similar to “reload” -> “capture” -> “reload” -> “capture” .. ?
(In other words, motor rotation speed can be measured correctly.)
Or will “reload” be executed again without “capture” after “reload”?
(In other words, capture data always becomes 0 because “capture” always be executed at the same time of “reloaded” at rising edge?)
Best Regards.
Yutaka Matsubara
Show LessI downloaded the official PSoC 4200 PCB footprint libraries for Allegro, Altium, and Pads and there does not seem to be an official footprint for the WLCSP 35-ball package (the FN package). I have the 4200 family datasheet (001-87197 Rev. *J), and there is a drawing of the package on page 38, but no corresponding footprint specification. I have read JEDEC Design Guide 4.18 per the instructions in the datasheet, but it (as expected) only describes the package, not the recommended PCB footprint. I, of course, have the die WLCSP package size and pad spacing from the datasheet, so that's not an issue. All I need is the recommended pad size to complete the footprint myself. Any suggestions?
Edit: I found an application note from Freescale (now NXP), AN3846: Wafer Level Chip Scale Package (WLCSP), from 2012 that provides guidance for their WLCSP packages for both PCB layout and manufacturing. There is a copy here:
https://www.mouser.com/pdfdocs/AN3846.PDF
They say their their solder balls are 0.250mm in diameter, but Cypress says theirs are 0.260mm. I am going to guess that if I scaled the pad sizes by 0.260mm/0.250mm = 1.04, that I would get the right pad sizes for the process specified by Freescale/NXP. It's a bit of a bummer that Cypress doesn't seem to have any guidance at all on this even though they provide WLCSP packaged chips.
Show LessI am using a Maxim Evaluation kit (MAX86161EVSYS) which comprises the CY5677 BLE dongle. I would like to understand if there is a test point on the CY5677 that indicates the receipt of data. I am seeking to synchronize the data stream coming off the MAX86161 via the CY5677 with another data stream and wondering about a logic condition I could use.
Your assistance is greatly appreciated
Show LessHi ,
I am using CY8C4128LQI-BL543 trying to measure the ECO frequency with a frequency counter. I am using the reference guide for it. unfortunately, there is not reference to how to route the ECO to the GPIO for measurement, although it is mentioned in the reference document that it is needed as part of the Xtal trimming
the reference document is here:
https://www.cypress.com/file/139476/download
and the reference for routing is here:
Show Less
Hello, I require a Bilateral switch as per a 4066, I have tried using the creation wizard, but limited editing of the functions prevents me from creating this component, is it possible, or is there an example in existence already?
Kind Regards
Show LessHi ,
For an application without having the ability to pair with the device (since we are using one Master phone to scan multiple peripheral sensors), we would like to use application level encryption. I know that encryption and decryption using SW is very long , therefore usually using HW block for that. Is there any way which I can use the encryption/Decryption HW block directly ?
Couldn't find any reference for it online.
Show LessHello, I need experts assistance for Pcap button layout.
Because of the limited board area, we plan to use 4-layer board for a 8 buttons, 5 LEDs and 2 connectors (have other PWM signal, LED signals......). see attached mechanical drawing.
Follow AN64846 <Getting Started with CapSense>, the top layer is CapSense; layer2 is CapSense traces; layer3 is hatching Ground; bottom layer is other components and traces.
Our mechanical design has 2 connectors exactly underneath 3 buttons. According to <Getting Started with CapSense>, it says:
.........
* Isolate switching signals, such as PWM, I2C communication lines, and LEDs, from the sensor and the sensor PCB traces. Do this by placing them at least 4 mm apart and fill a hatched ground between CapSense traces and nonCapSense traces to avoid crosstalk.
* Avoid connectors between the sensor and the controller pins because connectors increase CP and decrease noise immunity.
.......
With a hatching Ground plane layer3, Can the connector directly under the button? And should all other traces (on bottom layer) at least 4mm apart from CapSense (on top layer) and CapSense traces (on layer2)?
Thanks.
Chang Cao
Show Less