PSoC™ 4 Forum Discussions
When I2C slave read and write buffers operation ,the index is incremented。 I can't find a function to reset the array index in the CAT2 Peripheral Driver Library of MTB.
Show LessIn PSoC Creator, I can use the function CapSense_ GetCentroidPos get the slider position. but, in modustoolbox, I found no function that can get the slider position in the Capense Middleware Library. Excuse me, which function can be used to get the slider position!
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I'm using USB Audio code similar to the CY8CKIT_046_USB_Audio example project, in CY8C4246AZI-L433, and when the IN/OUT bandwidth is high, on one computer, in particular, the code will consistently lock up inside this loop:
/* Request for dynamic re-configuration of endpoint. */
USB_DYN_RECONFIG_REG |= USB_DYN_RECONFIG_ENABLE;
/* Wait until block is ready for re-configuration */
while (0u == (USB_DYN_RECONFIG_REG & USB_DYN_RECONFIG_RDY_STS))
{
}
This register is at memory location 0x402c0050, and when the PSoC is locked up in this loop, that location reads 0x00000003 = 0b00011:
- DYN_RECONFIG_RDY_STS = 0b0 = not ready for reconfiguration
- DYN_RECONFIG_EPNO = 0b001 = Endpoint 2 ("Use 0 for EP1, 1 for EP2, etc.")
- DYN_CONFIG_EN = 0b1 = enable the dynamic re-configuration for the selected EP
So we've enabled re-configuration on EP2 (IN audio) but it's not entering the ready state. Any idea why?
Before this happens:
- Data is flowing normally IN (EP2) and OUT (EP1), with feedback IN packets regularly (EP8)
- The IN packets start to become identical. Buffer is not being updated? This might actually be the root of the problem. They are still changing length, though, to maintain the correct sample rate.
- The feedback packets stop
- After another ~35 OUT packets on EP1, the OUT packets stop
- After another ~35 IN packets on EP2 (all of which are now identical), the IN and OUT interfaces are both put into zero-bandwidth mode
- The OUT interface is put into active mode
- OUT packets are transmitted on EP1
- Feedback packets are transmitted on EP8, all zeros
- After ~40 OUT packets on EP1, the firmware locks up in that loop, seemingly during reconfiguration of EP2.
I am learning CAPSENSE slide on the CY8CKIT-149. the routine and my owm project work normally in PSoC Creator IDE. In modustoolbox2.4 IDE, The CAPSENSE_CSD_Slider_Tuning routine work normally。 I created a project according to this routine. In the Capsense tuner, I checked, but there was no response. After debugging, I found that the function Cy_ CapSense_ Enable return value is CY_CAPSENSE_STATUS_INVALID_STATE. Why CAPSENSE fails to enable?
I am attaching project .Thank..
Regards,
Show LessSpecifically, every time I start a new Debug session, I need to redo the following:
Display Watch 1 (Debug->Windows->Watch->1)
Display Watch 2 (Debug->Windows->Watch->2)
Change Memory 1 window to show 16 columns.
Reposition all debug windows in IDE.
Why do I need to disrupt my workflow and redo this manual work every time I enter a debug session? The IDE remembers the state and position of other windows, so why not the debug windows?
PSoC4のSWDポート 未接続時の処理につきまして、
1)量産の際にSWDポートをSWD設定のままにしておきたい場合、何か問題はあるでしょうか。
問題がある場合はその対処方法などございますでしょうか。
2)そもそもの話になるかもしれませんが、SWDポートは量産時(未使用時)はGPIO設定にしておくのが
推奨ということになりますでしょうか。
https://community.infineon.com/t5/PSoC-4/About-processing-of-debug-pins-SWDCK-SWDIO/m-p/29115
上記トピックに近いところとは思うのですが、
そのままでもいいかどうかなどの判断ができなかったため、
質問させていただきたく、よろしくお願いいたします。
Show LessPSoC4にて、設計時はデータ取りの為にI2Cとしているポートがございます。(miniprog3にてPCと接続)
このポートを量産などではLow出力にすることを検討しています。
物理的にはminiprog3とLow出力が繋げられる形なのですが、万が一接続した場合、
PSoC4もしくはminiprog3が破壊される可能性はありますでしょうか?
ポートのDrive modeによって違う、などの情報もあればご教示いただきたく、よろしくお願いいたします。
Show Less当我使用CY8C4146LQS-S423芯片的AD采集功能时,遇到一些问题。当电压值在6V时,采集到AD值大约是6.6V (0x0349),偏差会很大。并且外部供电越小,采集到的AD值偏差越大。
最开始我使用的配置如下:
因为被建议使用内部Verf提高AD采集精度,所以我尝试修改VDDA/2为Internel 1.024 volts,似乎我使用的芯片不支持这么设置。
然后我将VDDA/2改为Internel Vref,似乎出了什么问题,设备不能正常运行了。
所以这个偏差我该怎么使它变小一些?之前有提问过AD采集不准确的问题如下:
https://community.infineon.com/t5/PSoC-4/PSoC4-AD-value-not-correct/td-p/375154
另外附上AD采集的分压电路:
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