PSoC™ 4 Forum Discussions
I am looking for a Creator project that uses the Senzei Component, all the sensing projects are using a different component.
Thanks
I am playing around with a design involving a PSOC4100 BLE (specifically, the CY8C4127LQI-BL453) and am trying to sort out some issues I have with current drain when I trigger my design out of Hibernate mode with a signal on one of the GPIO.
Firstly (and this has tripped me up before) I am having to deal with the section of code Cypress have written that deals with chip initialisation.
In cyfitter_cfg.c, where the WCO is being set up (assuming its been enabled), there is a call to:
CyDelayCycles(12000000u); /* WCO may take up to 500ms to start */
This basically just stuffs in a 500msec delay during startup, which means my code isn't actually being run for the first 500msec. If I disabled the WCO, and rely on the ILO instead, then I can reduce that start up time to about 30msec, which is much more managable. But, I wanted to know:
1. Is the WCO only needed if I am firing up BLE and/or using the WDT? If so, then I'm OK to not even enable it for most of the situations where I come out of Hibernate, as I'm not using either of these functions in my code at that point
In addition, looking at the current on startup, I'm seeing an average of about 7mA drain for the first 25msec, with a spike of about 20mA for a 3msec period at about 15msec after start up. This then drops down to about 3.5mA once my code starts up. I'm trying to reduce the current drain in that first 25msec to something lower, as its putting too much demand on my battery, which is causing a significant droop in VCC. I could put some additional capacitance across VCC to try and take some of the load off the battery, but tantalums and ceramics are notoriously leaky (for example, a 100uF, 6.3V ceramic has a typical leakage of ~ 6uA, and in Hibernate mode my circuit is drawing about 500nA, so I can't really afford that option) so I'm wanting to try and spread the start up current out over a longer period so I can reduce the peaks.
2. Does anyone know what's causing the chip to have that current spike of around 20mA during the startup sequence? I'm trying to understand where its coming from, to see if I can either eliminate it, or reduce it somehow.
Regards,
Mike
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Hi!
Is there any way to update the firmware as the CySmart does but using a batch file with the appropiate commands ?
Environment: PSoC Creator 4.4, CY8C4147AZI-S465
I'm going into the infinite IntDefaultHandler and seeing ENOMEM when calling srand() or rand() without heap.
Since I'm currently not doing any other dynamic memory allocation if I run the same code without calls to srand() and rand() the code runs fine, even without any heap.
Is it expected per the C standard?
I tried to run the exact same test of running srand() and rand() without heap on a TI F28002x and it runs fine, although of course rand() isn't actually returning a random number.
My fear is that srand() and rand() are unsafely using the heap in PSoC 4's implementation.
hello,I‘m user of CY8C4014LQI-421_16-QFN. I have two questions about it .
- about the power supply mode.
"There are two distinct modes of operation. In Mode 1, the supply voltage range is 1.8 V to 5.5 V (unregulated externally; internal regulator operational). In Mode 2, the supply range is1.8 V ±5% (externally regulated; 1.71 to 1.89, internal regulator bypassed)."
I want to know that which mode has stronger robustness?If I use the mode 2,what the pitfalls might it has?
- about the I2C
If I power the VDD=3.3V .what the high threshold and low threshold are?
3.3V*0.7and3.3V*0.3?
OR 1.8V*0.7and1.8V*0.3?
thanks!
Show LessHello,
The capsense slider of the CY8CKIT-149 is implemented with a Tx pin , which is required in the mutual capacitive sensing (CSX) mode. On the PCB design, the TX trace is distributed between every segment. So hardware is OK for a slider in CSX mode. However when I checked in the "CE220891_CapSense_with_breathing_LED" project with PSCOC Creator, there is no other choice but CSD (self capacitance) for slider.
I don't understand.Is it possible to configure slide in CSX mode? If no, why is the CY8CKIT-149 hardware implemented for It?
Best Regards
Show LessHello!
In the process of studying Bootloader\Bootladable projects, I noticed that bootloadable link script can improved (I thin so).
Original part is:
...
.bootloader_data (NOLOAD) : ALIGN(8)
{
. += BOOTLOADER_RAM_SIZE
}
...
Supposed improvement:
.bootloader_data (NOLOAD) : ALIGN(8)
{
. = BOOTLOADER_RAM_SIZE - SIZEOF(.ramvectors) - SIZEOF(.btldr_run);
}
As a result we can remove the memory leak of ~ 200 bytes.
Or may be I 'm wrong?
Thanks.
Show LessHello,
I am implementing a slider design following the "AN85951 PsoC4 and PSoC6 MCU CapSense Design Guide".
On the CYC8CKIT-PSOC149 development kit , buttons and slider are covered by solder mask, copper is coated. Hower it is not mentioned in "AN85951 PsoC4 and PSoC6 MCU CapSense Design Guide" that copper should be covered by solder mask.
Is it required to cover copper with solder mask? If so then what is the consequence on the capacity sensor?
Best Regards
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Dear Sirs and Madams,
We are considering using WDT function for PSoC4S.
I set the "Timer (WDT)" on the "Configure System Clock" screen as shown below.
So we have some questions.
(1)
Is it necessary to set the "WDT_MATCH" register in the program even if the above settings are made in the GUI?
(a) No WDT_MATCH setting *IGNORE BIT(19-16bit) 3H
Probably the above is the initial value.
(b) With WDT_MATCH setting (set 1FFFH(8191D)) *IGNORE BIT(19-16bit) 3H
(2)
Even if you set the WDT on the GUI, if the WDT_MATCH register setting process is required in the program of main.c, zWe don't know the reason for setting "Period" on the GUI.
(3)
When will the WDT count start?
Is it the timing when the CySysWdtEnable API is called in PSoC4S?
Are there any other conditions for the WDT count to start?
Regards,
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Hello ,
I am trying to send my data from the encoder to my cy8ckit-043 to check for any errors along with my CRC polynomial. How do I set it up in my PSoC creator. I made a CRC table in PSoc and wrote my polynomial representation too. I am still confused how to check for crc . I would like to know about the seed value and my polynomial value, what do they generate? How should I send my data stream through di pin on crc?
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