I'm working on a design that needs a 25 bit shift register with PLD output taps at 0, 8, 12, 16 and 24.

First stage is a D-FF.  But it appears that a 24 bit UDB SR can't provide taps, nor can 3 8 bit UDB SRs provide the 12 bit tap.  So my architecture is D-FF, SR 8, 8 D-FFs, SR 8.  Now the questions:

1.  When I designed it, the build tool gave me a warning about async clock crossings.  All of the above is connected to a single clock, yet the SR 8 outputs are, it claims, clocked from CyHFC.  I'm a bit lost on how that got there.

2. Using the above topology, the tools are going to use duplicate macro blocks for the two SR 8s, which would have been combined if I had used an SR 24.  Further, there is no need for load, store or reset, so it really shouldn't need any macro cells.

3. I'd probably be better off just configuring two UDBs, but I haven't figured out how to do that (how to get symbols to place on the schematic.

4.  I'd probably prefer to do the whole thing in Verilog and forget the schematic, but I haven't been able to find a Verilog primitive for the UDB.  Presumably there is one for the ALU and separate ones for the counter and other parts, possibly even for the Control, Status and FIFOs, which aren't needed in this part of the design.

5. The UDB document claimed there would be a tab at the bottom of the schematic to access the Verilog code generated by the page.  I had hoped I could use that as a model for any or all of the above shortcomings, but no such tab appeared.

I'm fairly proficient at hardware design and Verilog (not to mention embedded firmware development, but this is my third experience with PSoC Creator and my first experience with UDBs, so I'm in a learning curve.  I did build one sample project to get me oriented.

I have attached a screen shot of the intended design.  It is part of a larger hardware design for a 4200L