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Simplest PSOC3 project won't fit into PSOC4.
I'm wondering how flash size of 32KB compares to 32KB of PSOC3.
I think PSOC3 flash is 2 times more efficient ( smaller instructions).
I think PSOC4 should be called ADCWLE (ADC with little extra).
Regards
Robert
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I am not so sure you are correct about code density -
www.arm.com/products/processors/cortex-m/cortex-m0.php
Of course at ~ 1/2 to 1/5 cost of a PSOC 3 you do give up something, so pick
design target for PSOC 4 with that in mind. Side by side design requirements vs
capabilties is clearly how you would decide.
Regards, Dana.
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There will always be projects suitable to a cheap cortex m0 cpu.
The cost plus having a project with a small cpu with i capable of being upgraded to a bigger psoc is a good reason to use it.
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The question could have been as well as "Who needs PSoC1" The fact is, there are more PSoC1s sold than PSoC3 + PSoC5. So a new family introduced with limited but extreme flexible hardware inside and a more modern CPU defitively WILL find its market.
Bob
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If we presume, that PSOC4 is targeted to STM Family Customers, it's a blind shot.
The STM gives more flash, which is very important, if You have nothing else available (except ADC).
The big advantage of PSOC1 & 3 & 5 was a hardware multitasking. Processor on one end, timers etc on the other.
They might've been working totally separate (as I understand PSOC).
Psoc4 lost all the advantages, because of very tiny hardware.
I was rather expecting POSC4 as a clone POSC1 plus debugger. Nothing like this happened.
POSC4 goes it's own way, where then name PSOC in front is very misleading.
REgards
Robert
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So it is marketed between PSoC3 and PSoC5.
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I think position in roadmap simply adjacent to PSOC 5 due to core is same.
Stated another way a low end ARM family.
Based on architecture, cost, density, it's sorta in its own unique position.
Regards, Dana.
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If it is cheaper than PSoC3, I think people would prefer to use this more then PSoC3.
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We have a project that use PSoC1 now and needs to add more features to it for next relase. Would be good if the bigger PSoC4 be avaiable sometime this year.
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PSOC 4 cost basis is < PSOC 3.
Design constraints will determine use of 3 or 4 in a design.
Lastly you can contact Cypress local field sales office or manufacturers representative
to get an idea of release dates for other PSOC 4 devices.
Regards, Dana.
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HI Dana,
The project would not be started this year, so no rush yet. But would like to have the data sheet of the whole series.
🙂
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SAR + 32 bit multiplier + code + IDAC = Filter
SAR, 12 bits, .1% G error, over temp & Vdd, ~2 - 3 LSB error, not bad precision.
Not 20 bits, but then where is the data to support 20 bits over T & V........
Regards, Dana.
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Most embedded MCUs don't really need PC connectivity - thats why they are embedded... The PSoC4, esp. when the larger families are not so expensive, can be a good replacement for the PSoC3 when more processing power is needed. Or for the PSoC5 when this one is too expensive.
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It would be an interesting survey as to what % units shipped connect to PC via USB or Serial.
Cell phones USB centric, they would be one dominant influencer i that study. IPOD, IPAD,
GPS, test, measurement, toys...... most need and use connectivity.
As far as PSOC 4 replacing PSOC 3, certainly the core cpu is a plus, but HW restrictions,
number UDBs not so sure. There is of course TCPWM unit that is not in PSOC 3, in
some situations helps to make up for the UDB deficit in PSOC 4. But design criteria would
drive whether a 4 could replace a 3.
Regards, Dana.
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Most designs I have seen don't use USB communications. USB is a segment of the market, I don't think its a main driver. in the recent years has been a trend to connect everything to a computer but even then other communications channels are often used (wireless , other serial protocols)
Most Cell phones and PAD like devices run on Applications processors and only use an mcu connected to the main processor where usb has no place.
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Some stats, much more detail via google www.zdnet.com/blog/btl/usb-holds-steady-as-most-successful-interface-ever/61023
As a FAE over the last decade I saw USB applications grow from ~ 5% of the designs to
>> 50% when I left in 2008.
Clearly we see two different markets.
Regards, Dana.
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Most probably. I deal mostly with industrial an automotive in the field. Znet and its stats deal mostly with PC peripherals and consumer electronic and talks about all USB in general.
Although, I have to agree that a single design win in a CE device like the iPad or iphone would represent more psocs shipped than all control, wireless sensor or all industrial applications together. But then in such devices its the apps processor in charge of usb. The microcontroller is in charge of buttons, capsense, vibrating motors rather than USB
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IMO - > Advantage - Low cost and reasonable core. Disadvantage -> Limited UDB's
I want Cypress to do a PSoC 1 with upgraded MCU - The M8 is too slow to be really useful, but the UM blocks are great.. Something like a full PSoC 1 archetecture with the Arm M0 core would, IMO, be more valuable..
As said somewhere above - the biggest sales are still PSoC 1 - So no need to change anything except the core.. Those developing PSoC 1 have the tools already, bring the new chips out with the same footprints as the PSoC 1, and people like me who have invested in obtaining the full PSoC 1 DK can use this kit and develop more advanced applications.
Just like the AWFUL "express" idea (which was a complete waste of everyones time), Cypress is, IMO, missing the obvious - The money is from developers like me who design PSoC into clients products for the mass market .. PSoC 4 goes some way towards what is needed.. But as soon as one has a project where (due to lack of on-chip blocks) one is forced to add external hardware, the main reason for selecting PSoC becomes weaker - Using a standard MCU with some external can be lower cost.
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Simply put the PSOC 1 ICE Cube would not work with the Coretex M0 debug
architecture, so you are stuck. But then debugging an M0 only requires a simple
board, or your proto, as debug HW is on chip on the M0. JTAG and SWD are
supported.
I agree, I was looking forward to a PSOC 1 with M0 core and more FLASH. But
on close examination I think I can do what needs to be done in PSOC 4 and
frankly Creator is a major step above in tools over Designer.
Regards, Dana.
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We used PSoC1 in a few projects. But we switch to PSoC3 and PSoC5 for our new pojects, one of the reason is it need more flash for program but at the same time, the SWD/JTAG debugger is a much better way for project developemnt. For PSoC1 we have to use the ICE club and different chip has different foot, and soldering those foot is not extremely hard but not easy. and the ICE club seems to be a bit fragile( we have a few dead club). Our design is not in high volume, so the need for the cheapest chip is less important, the boss rather have to have the product quicker.
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I have now played with 4 on the pioneer kit..
Greatly dissapointed - there just isnt enough in it to make it useful for anything but the simplest projects IMO..
And I am puzzled - It seems that either the fitter is not using all available resources, or that there are some strange limitations in the PLD blocks..
Ok - Only been playing for a couple of days.. I may find ways to pack more in by careful selection and re-design.. But so far I am seriously unimpressed.. And puzzled.. A design using eight T FF's and one D FF, 4 XOR's and one 2in OR was not able to fit - "Requires 5 UDB's" but using two 8 bit UDB PWM's and the gates and a D FF fitted..
Also, I have not found any resources "monitor" in creator - If one has to squeeze the resources, some simple way of showing what percentage of each particular resource has been consumed would be a great help.
One other thing / question.. Are the PLD blocks similar to those in PSoC 3 and 5 in any way ? I have not done a lot with these parts, but from what I have done it seems to me that they are completely different animals.
Anyway, I am reasonably sure that PSoC 4 wont do what I need even for my simplest projects - my test project was about 1/3rd of what I usually need, and can easily do in PSoC 1, and if I need a faster MCU the PSoC 3 is great, and PSoC 5 for really meaty projects that can take the cost.. Its a shame, but 4 is hyped up to be something its not me thinks..
Lets have an example project where the 4 is packed to capacity, so we can see what it can REALLY do.. LED blinking and capsense with LED being PWM'ed dont really show its potential - or do they !?
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Every part/familiy has a place. Seems like everyone wants PSOC 4 = Cray Computer.
The 4200 family has ( which all other familes do NOT have )
1) 32 x 32 single cycle multiplier
2) TCPWM block, apart from UDBs, 4 16 bit PWM/Counter/Timers. How many UDBs is that worth in many designs ?
In UDB count does that ~= 8 UDBs equivalency ?
3) Parts down to a buck, $ 1 (maybe PSOC 1 has some parts close to a $ 1)
4) Great core, M0, thumb mode, eat that 8051, and the core has a linear address space, thank you Buddha
I think there is a ton of designs this family can do, and wonder if it will, in the not too distant future, outship
unit wise PSOC 3/5.......
Regards, Dana.
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Dana is right. Also, the dedicated serial comm module will save some UDBs. I'm sure almost all designs use a least 1 seral interface be it SPI , I2C or UART.
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Thanks Zeta for pointing SCB out.
So now looks like we have a UDB equivalency of 10 UDB blocks, for $ 1, in the 4100 family,
so thats ~ 10 cents/UDB.
Compare that to PSOC 3/5 24 UDBs for $ 5 = 21 cents/UDB, cowabunga buffalo bob,
I think all my designs will be multi processing PSOC 4 from here on out......
Tounge in cheek.....
Regards, Dana.
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- there is an *.rpt file in the project directory, which contains the report of the cyfit process. It contains also a report of how many resources are used (I think it is usual about 2/3rd down).
- The 4200 has 4 UDBs with 2 Macrocells each, so you have a maximum of 8 FFs available - how did you expect to fit 9 of them into it?
- 2xUDB-PWM uses 2 UDBs, the DFF needs 1/2 UDB, so it will fit in (you left out 8 FFs...)
- (and 5 gates fir easily in the available macrocells)
- and the PSoC4 hasd the TCPWM block which are more capable than the fixed function PWMs of th PSoC3/5
- the PLD blocks are the same as for PSoC5LP AFAICS
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1) 32 x 32 single cycle multiplier
2) TCPWM block, apart from UDBs, 4 16 bit PWM/Counter/Timers. How many UDBs is that worth in many designs ?
In UDB count does that ~= 8 UDBs equivalency ?
3) Parts down to a buck, $ 1 (maybe PSOC 1 has some parts close to a $ 1)
4) Great core, M0, thumb mode, eat that 8051, and the core has a linear address space, thank you Buddha
•there is an *.rpt file in the project directory, which contains the report of the cyfit process. It contains also a report of how many resources are used (I think it is usual about 2/3rd down).
•The 4200 has 4 UDBs with 2 Macrocells each, so you have a maximum of 8 FFs available - how did you expect to fit 9 of them into it?
I think all my designs will be multi processing PSOC 4 from here on out......
------------------------
Points taken.. And yes, the low cost does make it feasable to use multiple parts in a design.. Two 4200's clock in at about the price of a CY8C29466 (or cheaper), and one does have the huge advantage of the M0..
Fred.
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dana really?
trolling on a forum like this? you know better
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Hmm, using multiple PSoC4s together sounds like a great idea. It might be a good idea to have a special component (based on I2C maybe to allow multi-master) which handles all the communication between them...