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PSoC™ 4

lola_1650581
New Contributor II

Hi:

    The SCB interrupt  has the follow register:
   SCB0_INTR_TX,SCB0_INTR_TX_SET,SCB0_INTR_TX_MASK,SCB0_INTR_TX_MASKED

  I found that when a tx interrupt  happened which only the NOT_FULL bit has been enabled,the value of SCB0_INTR_TX    and SCB0_INTR_TX_MASKED are different.Show bellow:

pastedImage_0.png

   Can you help me explain their role and differences?Why the the value of SCB0_INTR_TX is 0x00000412 ,but        the SCB0_INTR_TX_MASKED is 0x00000002?

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1 Solution
Bob_Marlowe
Expert II

The value of SCB0_INTR_TX gets ANDed with the interrupt mask. The result is 0x02 showing the NOT_FULL interrupt was fired.

Bob

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3 Replies
Bob_Marlowe
Expert II

The value of SCB0_INTR_TX gets ANDed with the interrupt mask. The result is 0x02 showing the NOT_FULL interrupt was fired.

Bob

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lola_1650581
New Contributor II

Hi Bob:

     Why the the value of SCB0_INTR_TX is 0x00000412?

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HeLi_263931
Honored Contributor II

According to the PSoC4 register TRM these bits are set in SCB_INTR_TX with 0x0412:

  • NOT_FULL (the '2')
  • EMPTY (the '1')
  • UART_ARB_LOST (the '4')

The latter one is from the PSoC4000 register TRM, its not in the PSoC4100/4200 register TRM. IF yoiu have further questions about the specific bits, please look at the TRM and the register TRM for your device.

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