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KevinR_91
Employee
Employee
25 replies posted 10 likes received 10 replies posted

Can Cypress please provide the following properties for the LIN 2.1 interface on PSoC4S Plus??

How many elementary parts is the bit divided?

How many bit-samples do you use?

What is the sampling point position?

What is the rule to decide the bit level?

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harshadap_76
Employee
Employee
First like received

Hi Kevin,

In physical layer the bit pattern for LIN is same as UART.  Thus the over sampled at 16x. The sample point is middle of bit.

By 'elementary parts' do you mean different threshold levels of LIN bit on LIN bus?

The decision regarding bit level and thresholds of the bit on the LIN bus is taken care by the tranciever as per LIN spec. The tranciever is outside PSoC.

The tranciever converts LIN bus signal level to Micro-controller logic level which is readable by PSoC.

Hope this helps.

Please feel free to ask for any clarification.

Regards

Harshada

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harshadap_76
Employee
Employee
First like received

Hi Kevin,

In physical layer the bit pattern for LIN is same as UART.  Thus the over sampled at 16x. The sample point is middle of bit.

By 'elementary parts' do you mean different threshold levels of LIN bit on LIN bus?

The decision regarding bit level and thresholds of the bit on the LIN bus is taken care by the tranciever as per LIN spec. The tranciever is outside PSoC.

The tranciever converts LIN bus signal level to Micro-controller logic level which is readable by PSoC.

Hope this helps.

Please feel free to ask for any clarification.

Regards

Harshada

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