Variations in output slew rate on PSoC pins.

[GrCa_1363456]

Does transparent mode, in the Output section of pin Configuration, affect drive strength or ramp time on PSoC 4?

I.E. Does the addition of syncronization increase the drive strength?

I'm specifically interested in 48-TQFP PSoC 4200L GPIO pins.

I'm seeing a slow fall time on P1.6 in a TQFP-48 pin PSoC 4200L (CY8C4246AZI-L433). The drop time when switching from 3.3V to 0V speeds up when Clock is selected as output mode for the pin instead of Transparent.

Greg

[Len_CONSULTRON · Accepted solution]

Greg,

I don't work for Infineon so take my answers with that in mind.

My assumption for your questions are using P1.6 as a digital output with the Drive mode = STRONG.

Does transparent mode, in the Output section of pin Configuration, affect drive strength or ramp time on PSoC 4?

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No.   The STRONG mode push-pull (totem) configuration is either drive strong LOW or strong HIGH.

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I.E. Does the addition of syncronization increase the drive strength?

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No.  The only difference is the addition of a DFF latch in front of the output driver.

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...

I'm seeing a slow fall time on P1.6 in a TQFP-48 pin PSoC 4200L (CY8C4246AZI-L433). The drop time when switching from 3.3V to 0V speeds up when Clock is selected as output mode for the pin instead of Transparent.

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Can you supply the fall time of P1.6 in transparent mode and in sync mode?   What is your effective capacitance on P1.6?

[GrCa_1363456]

Len,

Thanks for the thoughts. I noticed in your response you compared Transparent to Sync and not to Clock.

My question is what changes between Transparent and Clock Output Modes.

Aside: This got me second guessing myself, so I tried to recreate the conditions in a new project.

The project I see a timing difference in uses Output Mode of Clock versus Transparent.

I have NOT been successful making a second project that will accept output mode of “Clock” on an Output pin. I'm not clear what the process is to enable a successful build with an output mode set to "Clock".

The error I get is: sta.M0021:Warning-1350: Asynchronous path(s) exist from “Clock(FFB)” to “CyHFCLK”. See the timing report for details

Timing report shows timing violation of Source Clock “Clock(FFB)” to Destination Clock “CyHFCLK”

[Len_CONSULTRON]

Greg,

On my test project using a 4200-series part I get these choices for output mode:

I think we may have an answer.

Here is an excerpt from the datasheet of a Digital Output.

Output Mode
Output synchronization reduces pin-to-pin output signal skew in high-speed signals requiring minimal signal skew. By default, this parameter is set to "Transparent" and no synchronization occurs. If "Single-Sync" is selected, the output signal is synchronized to the output clock.
▪ Transparent – Default
▪ Single-Sync
▪ Clock (PSoC 4 only)
▪ Clock-Inverted (PSoC 4 only)
On PSoC 3 and PSoC 5LP, the output clock is always BUS_CLK.
On PSoC 4, the output clock defaults to HFCLK, but may be changed via the Out Clock parameter.
Choosing either "Clock" or "Clock-Inverted" output modes on PSoC 4 allows the externally connected clock or signal to drive the pin. In this configuration, the data register (DR) value is used as an enable to the out_clock terminal and must be set high either by initially setting it to 1 in the pin customizer or set using software. Note that if this is a HW output pin then the value of the signal connected to the output pin terminal does not affect the operation of the pin when in this mode. Instead, hardware control of the clock enable can be achieved if Out Clock Enable is used with DR set high.

By syncing the output to the clock allows for a faster slew rate.

In the datasheet there are references to Fast Strong and Slow Strong rise and fall times.   I don't know if these modes refer to Transparent as being slow strong and Clock sync'd as fast strong modes.