USBDEVv2_DYN_RECONFIG isn't reaching ready status

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JoBr_1593366
Level 5
Level 5
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I'm using USB Audio code similar to the CY8CKIT_046_USB_Audio example project, in CY8C4246AZI-L433, and when the IN/OUT bandwidth is high, on one computer, in particular, the code will consistently lock up inside this loop:

/* Request for dynamic re-configuration of endpoint. */

USB_DYN_RECONFIG_REG |= USB_DYN_RECONFIG_ENABLE;

/* Wait until block is ready for re-configuration */

while (0u == (USB_DYN_RECONFIG_REG & USB_DYN_RECONFIG_RDY_STS))

{

}

This register is at memory location 0x402c0050, and when the PSoC is locked up in this loop, that location reads 0x00000003 = 0b00011:

  • DYN_RECONFIG_RDY_STS = 0b0 = not ready for reconfiguration
  • DYN_RECONFIG_EPNO = 0b001 = Endpoint 2 ("Use 0 for EP1, 1 for EP2, etc.")
  • DYN_CONFIG_EN = 0b1 = enable the dynamic re-configuration for the selected EP

So we've enabled re-configuration on EP2 (IN audio) but it's not entering the ready state.  Any idea why?

Before this happens:

  • Data is flowing normally IN (EP2) and OUT (EP1), with feedback IN packets regularly (EP8)
  • The IN packets start to become identical. Buffer is not being updated?  This might actually be the root of the problem.  They are still changing length, though, to maintain the correct sample rate.
  • The feedback packets stop
  • After another ~35 OUT packets on EP1, the OUT packets stop
  • After another ~35 IN packets on EP2 (all of which are now identical), the IN and OUT interfaces are both put into zero-bandwidth mode
  • The OUT interface is put into active mode
  • OUT packets are transmitted on EP1
  • Feedback packets are transmitted on EP8, all zeros
  • After ~40 OUT packets on EP1, the firmware locks up in that loop, seemingly during reconfiguration of EP2.
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