USBDEVv2_DYN_RECONFIG isn't reaching ready status

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
JoBr_1593366
Level 5
Level 5
100 sign-ins 50 questions asked 100 replies posted

I'm using USB Audio code similar to the CY8CKIT_046_USB_Audio example project, in CY8C4246AZI-L433, and when the IN/OUT bandwidth is high, on one computer, in particular, the code will consistently lock up inside this loop:

/* Request for dynamic re-configuration of endpoint. */

USB_DYN_RECONFIG_REG |= USB_DYN_RECONFIG_ENABLE;

/* Wait until block is ready for re-configuration */

while (0u == (USB_DYN_RECONFIG_REG & USB_DYN_RECONFIG_RDY_STS))

{

}

This register is at memory location 0x402c0050, and when the PSoC is locked up in this loop, that location reads 0x00000003 = 0b00011:

  • DYN_RECONFIG_RDY_STS = 0b0 = not ready for reconfiguration
  • DYN_RECONFIG_EPNO = 0b001 = Endpoint 2 ("Use 0 for EP1, 1 for EP2, etc.")
  • DYN_CONFIG_EN = 0b1 = enable the dynamic re-configuration for the selected EP

So we've enabled re-configuration on EP2 (IN audio) but it's not entering the ready state.  Any idea why?

Before this happens:

  • Data is flowing normally IN (EP2) and OUT (EP1), with feedback IN packets regularly (EP8)
  • The IN packets start to become identical. Buffer is not being updated?  This might actually be the root of the problem.  They are still changing length, though, to maintain the correct sample rate.
  • The feedback packets stop
  • After another ~35 OUT packets on EP1, the OUT packets stop
  • After another ~35 IN packets on EP2 (all of which are now identical), the IN and OUT interfaces are both put into zero-bandwidth mode
  • The OUT interface is put into active mode
  • OUT packets are transmitted on EP1
  • Feedback packets are transmitted on EP8, all zeros
  • After ~40 OUT packets on EP1, the firmware locks up in that loop, seemingly during reconfiguration of EP2.
0 Likes
10 Replies
Ekta
Moderator
Moderator
Moderator
750 replies posted First like given 250 solutions authored

Hello JoBr_1593366 ,

Can you please attach your project as well as the steps to recreate this issue.

This will help us to get a better understanding of the issue.

Best Regards

Ekta

0 Likes

No, I can't post the project here.  It is the same project I have been asking you about by email.

I have noticed that the IN packets sometimes contain data from the preceding OUT packet, after the first 32 bytes, which must be because the data is still in the USBFS component's common area:

For IN transfers the DMA tries to fill the common area as much as possible to provide the USB block with data to send. The DMA also pre-loads 32 bytes into the endpoint buffer before allowing the host to start reading it. This action adds time for the DMA to write next chunks of the data while the host reads the pre-loaded data. In case the DMA fails to load data in time (before the host reads it), the old data which resides in the common area will be sent on the bus.

That explains why the first 32 bytes of the IN packet are being updated, but the remaining bytes are copied from the previous OUT packet:

OUT:

pastedImage_2.png

next IN:

pastedImage_1.png

So there is a problem with the DMA failing to load data from inRam to the USB component in time for the host to read it.  Do you know any reason why that might happen?

0 Likes

This code is also present in the CY8CKIT_046_USB_Audio project.  I was emailing with you 2020-02-06 about it but never got a response.

0 Likes

This is still a problem, do you have any idea why it's happening?  What would prevent the DYN_RECONFIG_RDY_STS bit from being set?

0 Likes

It looks like the documentation for this register is wrong, too.

PSoC 4200L Family
PSoC® 4 Registers
Technical Reference Manual (TRM)
Document No. 001-98126 Rev. *C
June 7, 2017

says:

  • DYN_RECONFIG_EPNO (bits 3-1)
    • These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1.
    • Default Value: 0
  • DYN_CONFIG_EN (bit 0)
    • This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1, indicates the reconfiguration required for selected EP.
    • Use 0 for EP1, 1 for EP2, etc.
    • Default Value: 0

I assume "Use 0 for EP1, 1 for EP2, etc." should appear under DYN_RECONFIG_EPNO, not under DYN_CONFIG_EN?

https://www.infineon.com/dgdl/Infineon-PSoC_4200L_Family_Psoc_4_Registers_Technical_Reference_Manual...

0 Likes

The original CY8CKIT_046_USB_Audio project had this code:

 

/* Select endpoint number of reconfiguration */
USBFS_DYN_RECONFIG_REG = (uint32) ((curEp - 1u) << USBFS_DYN_RECONFIG_EP_SHIFT);

/* Request for dynamic re-configuration of endpoint. */
USBFS_DYN_RECONFIG_REG |= USBFS_DYN_RECONFIG_ENABLE;

 

In this email from Ekta

Sent: Thursday, December 19, 2019 11:39 PM
Subject: RE: USB audio issues

it was proposed to combine these commands into one:

Also, Comment line 868 in USBFS_std.c. Change line 871 to this:

USBFS_DYN_RECONFIG_REG = USBFS_DYN_RECONFIG_ENABLE | ((uint32) ((curEp - 1u) << USBFS_DYN_RECONFIG_EP_SHIFT));

But this doesn't fix the issue.

In this email from Ekta

Sent: Thursday, January 9, 2020 1:06 AM
Subject: RE: USB audio issues

The file USBFS_ConfigAltChangedfixed.c contains the combined command and also a cast to void:

 

/* Set endpoint number and request dynamic re-configuration */
USBFS_DYN_RECONFIG_REG = ((uint32) ((curEp - 1u) << USBFS_DYN_RECONFIG_EP_SHIFT) |
                                     USBFS_DYN_RECONFIG_ENABLE);

/* Ensure that register is written due to bufferable writes */
(void) USBFS_DYN_RECONFIG_REG;

 

but this doesn't fix the issue either, it still locks up in the "Wait until block is ready for re-configuration" while loop, about 9% of the time.

Is there any documentation for how this register works or how it is meant to be used, other than the short descriptions in the Register TRM?

0 Likes

I tried writing to the register every time but it still gets locked up in this loop:

 

/* Wait until block is ready for re-configuration */
// Wait until DYN_RECONFIG_RDY_STS bit is set by the hardware
while (0u == (USB_DYN_RECONFIG_REG & USB_DYN_RECONFIG_RDY_STS))
{
    USB_DYN_RECONFIG_REG = ((uint32) ((curEp - 1u) << USB_DYN_RECONFIG_EP_SHIFT) | USB_DYN_RECONFIG_ENABLE);
    (void) USB_DYN_RECONFIG_REG;
}

 

Memory location 0x402c005a just holds 0x0f no matter what:

  • DYN_RECONFIG_RDY_STS = 0 = not ready for reconfiguration
  • DYN_RECONFIG_EPNO = 0b111 = 7 = EP8
  • DYN_CONFIG_EN = 1 = reconfiguration required

This always happens while the USB bus analyzer shows that the host is trying to set Interface 1 to Alternate Setting 2.  I'm not sure why this involves EP8, the feedback endpoint.  When it locks up, curEp is 8.

0 Likes

Same if I clear and reset the bit inside the loop:

 

/* Wait until block is ready for re-configuration */
while (0u == (USB_DYN_RECONFIG_REG & USB_DYN_RECONFIG_RDY_STS))
{
    /* Complete dynamic re-configuration: all endpoint related status and signals
    * are set into the default state.
    */
    USB_DYN_RECONFIG_REG &= (uint32) ~USB_DYN_RECONFIG_ENABLE;
    (void) USB_DYN_RECONFIG_REG;
    
    USB_DYN_RECONFIG_REG = ((uint32) ((curEp - 1u) << USB_DYN_RECONFIG_EP_SHIFT) | USB_DYN_RECONFIG_ENABLE);
    (void) USB_DYN_RECONFIG_REG;
}

 

The memory location just alternates between 0x0e and 0x0f.

Adding delay doesn't fix it either:

 

while (0u == (USB_DYN_RECONFIG_REG & USB_DYN_RECONFIG_RDY_STS))
{
    CyDelayUs(100);
}

 

Is there a way to timeout this loop and try again?  I'm not sure what it would do to try again, though.

 

0 Likes

Can you please address this issue?  It's been years...

0 Likes
JoBr_1593366
Level 5
Level 5
100 sign-ins 50 questions asked 100 replies posted

Any updates on this?

0 Likes