UDB shift register

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Wilton
Level 4
Level 4
50 sign-ins 25 replies posted 5 solutions authored

I'm working on a design that needs a 25 bit shift register with PLD output taps at 0, 8, 12, 16 and 24.

First stage is a D-FF.  But it appears that a 24 bit UDB SR can't provide taps, nor can 3 8 bit UDB SRs provide the 12 bit tap.  So my architecture is D-FF, SR 8, 8 D-FFs, SR 8.  Now the questions:

1.  When I designed it, the build tool gave me a warning about async clock crossings.  All of the above is connected to a single clock, yet the SR 8 outputs are, it claims, clocked from CyHFC.  I'm a bit lost on how that got there.

2. Using the above topology, the tools are going to use duplicate macro blocks for the two SR 8s, which would have been combined if I had used an SR 24.  Further, there is no need for load, store or reset, so it really shouldn't need any macro cells.

3. I'd probably be better off just configuring two UDBs, but I haven't figured out how to do that (how to get symbols to place on the schematic.

4.  I'd probably prefer to do the whole thing in Verilog and forget the schematic, but I haven't been able to find a Verilog primitive for the UDB.  Presumably there is one for the ALU and separate ones for the counter and other parts, possibly even for the Control, Status and FIFOs, which aren't needed in this part of the design.

5. The UDB document claimed there would be a tab at the bottom of the schematic to access the Verilog code generated by the page.  I had hoped I could use that as a model for any or all of the above shortcomings, but no such tab appeared.

I'm fairly proficient at hardware design and Verilog (not to mention embedded firmware development, but this is my third experience with PSoC Creator and my first experience with UDBs, so I'm in a learning curve.  I did build one sample project to get me oriented.

I have attached a screen shot of the intended design.  It is part of a larger hardware design for a 4200L

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RodolfoGL
Employee
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250 solutions authored 250 sign-ins 5 comments on KBA

I would suggest to read our Component Author Guide (Menu Help > Documentation > Component Author Guide) to get started on developing custom components.

You could use the datapath of the UDBs to design exactly what you need. The datapath itself implements a shift register. You can refer to the implementation of the ShiftRegister component, which is built on top of the datapath. Refer to this post to learn how to import a component.

https://community.infineon.com/t5/PSoC-5-3-1/Importing-Component-into-PSoC-Creator-4-4/td-p/51056/pa...

The datapath has also an option to drive the ALU as parallel output, so you can route your intermediary signals (0 and 12) it out to the desired pins. 

In summary, you can implement this using three 8-bit datapath. Almost no macrocells required here.

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RodolfoGL
Employee
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250 solutions authored 250 sign-ins 5 comments on KBA

I would suggest to read our Component Author Guide (Menu Help > Documentation > Component Author Guide) to get started on developing custom components.

You could use the datapath of the UDBs to design exactly what you need. The datapath itself implements a shift register. You can refer to the implementation of the ShiftRegister component, which is built on top of the datapath. Refer to this post to learn how to import a component.

https://community.infineon.com/t5/PSoC-5-3-1/Importing-Component-into-PSoC-Creator-4-4/td-p/51056/pa...

The datapath has also an option to drive the ALU as parallel output, so you can route your intermediary signals (0 and 12) it out to the desired pins. 

In summary, you can implement this using three 8-bit datapath. Almost no macrocells required here.

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Wilton
Level 4
Level 4
50 sign-ins 25 replies posted 5 solutions authored

Thanks for the quick response.  The document is very helpful.  It answered more questions than I anticipated.  It didn't explain why the library SR seemed to be using a different clock than I connected.

The 24 bit data-path Verilog template in the document didn't have parallel outputs.  I don't know if that was an oversight, or if I need to instantiate three 8 bit data-path ALUs to get that.  I also realized that if I could tolerate a bit more propagation delay, I could configure a comparator to mask the bit 12 I need.

As for the bit 0, I can't avoid that FF.  There are actually 25 in the design, and I don't want to waste a fourth data-path just for one bit.

P.S.: (edit) I tried placing a udp document in a component.  It placed a udp8, which doesn't have parallel outs.  Can I add them and still call it a udp8? Or do I have to follow the component author guide and create a udp (base)?  It also put in a bunch of defines. I'm not sure if I need them if I roll my own from a base udp.  And it added an extra clock and used it instead of the one I wanted.

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RodolfoGL
Employee
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250 solutions authored 250 sign-ins 5 comments on KBA

When using the Datapath Config tool, there are five types of datapath you can add:

- cy_psoc3_dp : a raw 8-bit datapath that will have the parallel output signals

- cy_psoc3_dp8/16/24/32 : a chained datapath without the parallel outputs

If you configure a 24-bit shift register, it uses the cy_psoc3_dp24, that is why you don't see the parallel output. You have to add cy_psoc3_dp to see the parallel output, which only comes as 8-bit.

If you don't mind, can you share your project where you use the DFFs? We can look at why you are getting  the timing warning messages.

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Wilton,

It is my understanding that you are not writing to or reading from the shift register, but using it for a sort of a "mark detection" in the digital stream, so the Shift register can be constructed out of DFFs only,  without using the UDP Datapath.  This, however, will consume over 75% of PSoC4 macrocells.

     As an alternative, one can make a shift register using a Sync components instead of DFFs. The Sync component operates similar to a pair of DFFs, but is uses a Status Register resources (not a PLD). Each Status Register can make up to 4 Sync components (equivalent to 8 DFFs)      

odissey1_0-1679514956292.png

The last image represent a custom Sync32, which is a compact version of the stock Sync component:

Sync32 custom component for PSoC5 and PSoC4 

 

Example of the 25-bit shift register constructed with Sync32 component, with outputs from the 0, 8, 12, 16 and 24 taps is shown below:

odissey1_1-1679514956302.png

  As shown, the shift register consumes only 1 macrocell (DFF) and 3 Status Registers (out of 4 total) of the PSoC4 (4200M). Depending of the needs, you can substitute some of the  Sync with DFFs to balance resources. No UDBs are spared.

  Project attached.