Hi,
We want to get below digital circuit running in deep sleep using LFCLK.
Is it possible to do that? Document shows it is not is there any workaround to get running this functionality in <8uA.
If not possible, Is there any ICs available to implement such logic with low power?
Any suggestions? we want to match bit pattern and wake up MCU on that event.
Regards,
Hardik Harpal
Hardik,
Here's a snip of a document "PSoC 4 Low-Power Modes and Power Reduction Techniques"
link: https://www.cypress.com/file/121271/download
This and more information such as a power estimator tool can be found at:
You can see that in Deep Sleep mode the UDB logic is in "Retention". This means the logic states of the DFFs before entering sleep are retained. However, the logic is dormant while in Deep Sleep.
There are external PLD devices that can operate while you're in Deep Sleep, however I imagine the quiescent current far exceeds 8uA for these devices.
I noticed the following about your design intent:
- you're using LFCLK to clock the DFFs.
- The DFFs are configured as a shift register.
- The downstream logic with the Control Register is intended to generate an isr to wakeup the CPU if the shift register pattern matches the value in the Control Register.
I hope I got this correct.
Let me post some observations/questions.
Is the input data at Pin_1 clocked by LFCLK also? If not, the data can easily get out of sync in the Shift Register configuration.
You may what to have the isr synchronized to LFCLK also. This is to prevent false glitches in downstream XOR and OR logic from falsely triggering an isr.
The isr component is special internal interrupt generation mechanism. It may not be available in Deep Sleep mode.
In general, your desired configuration should not be available in Deep Sleep.
However, take a look at the I2C component. There is a note in the low power application note about "SCB (I2C address match) wakeup in Deep Sleep. Maybe this could work for you.
You other choice is to wakeup on a transition on Pin_1 and allow the shift register to be filled. When filled and a match exists, keep the CPU awake. If no match, let the CPU go back to Deep Sleep.
Hardik,
Here's a snip of a document "PSoC 4 Low-Power Modes and Power Reduction Techniques"
link: https://www.cypress.com/file/121271/download
This and more information such as a power estimator tool can be found at:
You can see that in Deep Sleep mode the UDB logic is in "Retention". This means the logic states of the DFFs before entering sleep are retained. However, the logic is dormant while in Deep Sleep.
There are external PLD devices that can operate while you're in Deep Sleep, however I imagine the quiescent current far exceeds 8uA for these devices.
I noticed the following about your design intent:
- you're using LFCLK to clock the DFFs.
- The DFFs are configured as a shift register.
- The downstream logic with the Control Register is intended to generate an isr to wakeup the CPU if the shift register pattern matches the value in the Control Register.
I hope I got this correct.
Let me post some observations/questions.
Is the input data at Pin_1 clocked by LFCLK also? If not, the data can easily get out of sync in the Shift Register configuration.
You may what to have the isr synchronized to LFCLK also. This is to prevent false glitches in downstream XOR and OR logic from falsely triggering an isr.
The isr component is special internal interrupt generation mechanism. It may not be available in Deep Sleep mode.
In general, your desired configuration should not be available in Deep Sleep.
However, take a look at the I2C component. There is a note in the low power application note about "SCB (I2C address match) wakeup in Deep Sleep. Maybe this could work for you.
You other choice is to wakeup on a transition on Pin_1 and allow the shift register to be filled. When filled and a match exists, keep the CPU awake. If no match, let the CPU go back to Deep Sleep.
