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PSoC™ 4

wablc_2332316
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Using Psoc Creator 4.1 and CY84247 module on the CYKit-042. I am using P3.5 as uart tx via SCB1. Everything works fine w the UART, but I need to pull down the TX line for ~1sec to reset comms then turn back to UART TX. How do I reconfigure the P3.5 TX line as a GPIO line and then back to a TX line programmatically at runtime?

Thanks

Wayne

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wablc_2332316
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Thanks to e.pratt pointing me in the right direction I found reconfigure thread that has the same requirement as myself. I'm able to successfully;

-Set P3.5 (TX) to GPIO =

//reset required bits to make GPIO, note this changes RX pin to GPIO as well

CY_SET_REG32(CYREG_HSIOM_PORT_SEL3,CY_GET_REG32(CYREG_HSIOM_PORT_SEL3) & 0xFF00FFFF);

//next set desired mode

UART_tx_SetDriveMode(UART_tx_DM_STRONG);

-Drive P3.5 low =

//set drive level as desired

UART_tx_Write(0);

-Set P3.5 to UART TX =

//set required bits to revert GPIO back to UART

//prior to GPIO change CYREG_HSIOM_PORT_SEL3 was 0x00990000 per cyfitter.h

CY_SET_REG32(CYREG_HSIOM_PORT_SEL3,CY_GET_REG32(CYREG_HSIOM_PORT_SEL3) | 0x00990000);

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Anonymous
Not applicable

See this thread: Change SWD pins to GPIO at runtime

But, to summarize it here:

"You may set the drive mode of a pin at any time using the appropriate Pin_SetDriveMode() API." @user_1377889

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wablc_2332316
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Thanks, the link was not clear to me how to address my issue. I read the UM re Pin_SetDriveMode() and still not understanding how to use this in a practical manner

Pin_1_DM_STRONG Strong Drive

Pin_1_DM_OD_HI Open Drain, Drives High

Pin_1_DM_OD_LO Open Drain, Drives Low

Pin_1_DM_RES_UP Resistive Pull Up

Pin_1_DM_RES_DWN Resistive Pull Down

Pin_1_DM_RES_UPDWN Resistive Pull Up/Down

Pin_1_DM_DIG_HIZ High Impedance Digital

Pin_1_DM_ALG_HIZ High Impedance Analog

I assume the parameter PIN_1_DM_STRONG would actually be PIN_5_STRONG, but how do pass/select the port? Once changed to GPIO how to return the port/pin back to uart?

Can you give a code example;

-Set P3.5 to GPIO

-Drive P3.5 low

-Wait 1sec

-Set P3.5 to UART TX

Thanks for your help

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wablc_2332316
Level 3
First like received First like given
Level 3

Thanks to e.pratt pointing me in the right direction I found reconfigure thread that has the same requirement as myself. I'm able to successfully;

-Set P3.5 (TX) to GPIO =

//reset required bits to make GPIO, note this changes RX pin to GPIO as well

CY_SET_REG32(CYREG_HSIOM_PORT_SEL3,CY_GET_REG32(CYREG_HSIOM_PORT_SEL3) & 0xFF00FFFF);

//next set desired mode

UART_tx_SetDriveMode(UART_tx_DM_STRONG);

-Drive P3.5 low =

//set drive level as desired

UART_tx_Write(0);

-Set P3.5 to UART TX =

//set required bits to revert GPIO back to UART

//prior to GPIO change CYREG_HSIOM_PORT_SEL3 was 0x00990000 per cyfitter.h

CY_SET_REG32(CYREG_HSIOM_PORT_SEL3,CY_GET_REG32(CYREG_HSIOM_PORT_SEL3) | 0x00990000);