Two SPIs (One Master and One Slave) in PSoC4

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ShVy_264716
Level 4
Level 4
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I want to implement a project of two SPI Peripherals communicating with each other in a single PSoC4. As a first step, I will send a character string from Master to Slave and the Slave has to receive it correctly. I need help from someone who can give example code for this. Thanks in advance. Shaunak. https://tinu.live/

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Anonymous
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Hello Shaunak,

The status cell count is related to the UDB (User Defined Block) which are general purpose circuitry used to implement hardware functions using verilog. The SPI components utilize theses UDB blocks to realize the SPI functionality without using CPU time/software code.

Each IC has a limited number of UDBs built into it at the factory, and the number is based on the specific chip. The chip you are designing for only has 4 UDBs that are Status Cells. The attached picture shows where you can look at the current project usage of the hardware resources in this respect.

Essentially, the SPI modules use 3 cells each, and the UART probably uses 1. But you should be able to see upon successful project build with the peripherals included.

There are multiple SPI peripheral modules defined, some of them may use less UDB cells (I have no idea which, if any, do)

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