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YoIs_1298666
Level 5
Level 5
250 sign-ins 100 replies posted 100 sign-ins

Hello,

I have two quesitons about PSoC4100S ADC SAR Seq.

1.About the converted resolution in case of each Single ended negative input for PSoC4100S.

 Is my understanding correct?

   [a. In case of "Vref select: VDDA/2 bypassed" and "Single ended negative input: Vref" ]

     The conversion resolution is 12bit.

pastedImage_2.png

   [b. In case of "Vref select: VDDA/2 bypassed" and "Single ended negative input: Vss" ]

    The conversion resolution is 11bit.

pastedImage_3.png

   [c. In case of "Vref select: VDDA" and "Single ended negative input: Vss" ]

    The conversion resolution is 11bit.

pastedImage_4.png

2.In case of [b in 1]., even if the analog input voltage exceeds Vref, is it not broken if it is below VDDA?

 Is the conversion result of the analog input voltage exceeding Vref Vref value?

Best regards,

Yocchi

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1 Solution

Ishii-san,

The analysis of [a, b, c] in your response#2 are correct.

And Yes. In case of [b in 1]., even if the analog input voltage exceeds Vref, is it not broken if it is below VDDA.

Regards,

Ryan

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4 Replies
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Yocchi,

From practical point of view it is probably irrelevant, as ADC last bit usually contains the noise.

/odissey1

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YoIs_1298666
Level 5
Level 5
250 sign-ins 100 replies posted 100 sign-ins

ello,

I have a misunderstanding for the following document.

pastedImage_0.png

It seems that the correct is understanding below?

[a. In case of "Vref select: VDDA/2 bypassed" and "Single ended negative input: Vref" ]

pastedImage_1.png

[b. In case of "Vref select: VDDA/2 bypassed" and "Single ended negative input: Vss" ]

pastedImage_3.png

[c. In case of "Vref select: VDDA" and "Single ended negative input: Vss" ]

pastedImage_1.png

2.In case of [b in 1]., even if the analog input voltage exceeds Vref, is it not broken if it is below VDDA?

From the datasheet, it seems that we can input up to VDDA.

pastedImage_5.png

Best regards,

Yocchi

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Ishii-san,

The analysis of [a, b, c] in your response#2 are correct.

And Yes. In case of [b in 1]., even if the analog input voltage exceeds Vref, is it not broken if it is below VDDA.

Regards,

Ryan

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Hello Ryan-san,

Thank you very much.

Best regards,

Yocchi

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